1 //===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetMachine and LLVMTargetMachine classes.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETMACHINE_H
15 #define LLVM_TARGET_TARGETMACHINE_H
17 #include "llvm/MC/MCCodeGenInfo.h"
18 #include "llvm/ADT/StringRef.h"
24 class InstrItineraryData;
31 class PassManagerBase;
34 class TargetELFWriterInfo;
35 class TargetFrameLowering;
36 class TargetInstrInfo;
37 class TargetIntrinsicInfo;
40 class TargetRegisterInfo;
41 class TargetSelectionDAGInfo;
42 class TargetSubtargetInfo;
43 class formatted_raw_ostream;
46 // Code generation optimization level.
47 namespace CodeGenOpt {
58 None, // No preference
59 Latency, // Scheduling for shortest total latency.
60 RegPressure, // Scheduling for lowest register pressure.
61 Hybrid, // Scheduling for both latency and register pressure.
62 ILP // Scheduling for ILP in low register pressure mode.
66 //===----------------------------------------------------------------------===//
68 /// TargetMachine - Primary interface to the complete machine description for
69 /// the target machine. All target-specific information should be accessible
70 /// through this interface.
73 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
74 void operator=(const TargetMachine &); // DO NOT IMPLEMENT
75 protected: // Can only create subclasses.
76 TargetMachine(const Target &T, StringRef TargetTriple,
77 StringRef CPU, StringRef FS);
79 /// getSubtargetImpl - virtual method implemented by subclasses that returns
80 /// a reference to that target's TargetSubtargetInfo-derived member variable.
81 virtual const TargetSubtargetInfo *getSubtargetImpl() const { return 0; }
83 /// TheTarget - The Target that this machine was created for.
84 const Target &TheTarget;
86 /// TargetTriple, TargetCPU, TargetFS - Triple string, CPU name, and target
87 /// feature strings the TargetMachine instance is created with.
88 std::string TargetTriple;
89 std::string TargetCPU;
92 /// CodeGenInfo - Low level target information such as relocation model.
93 const MCCodeGenInfo *CodeGenInfo;
95 /// AsmInfo - Contains target specific asm information.
97 const MCAsmInfo *AsmInfo;
99 unsigned MCRelaxAll : 1;
100 unsigned MCNoExecStack : 1;
101 unsigned MCSaveTempLabels : 1;
102 unsigned MCUseLoc : 1;
103 unsigned MCUseCFI : 1;
104 unsigned MCUseDwarfDirectory : 1;
107 virtual ~TargetMachine();
109 const Target &getTarget() const { return TheTarget; }
111 const StringRef getTargetTriple() const { return TargetTriple; }
112 const StringRef getTargetCPU() const { return TargetCPU; }
113 const StringRef getTargetFeatureString() const { return TargetFS; }
115 // Interfaces to the major aspects of target machine information:
116 // -- Instruction opcode and operand information
117 // -- Pipelines and scheduling information
118 // -- Stack frame information
119 // -- Selection DAG lowering information
121 virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
122 virtual const TargetFrameLowering *getFrameLowering() const { return 0; }
123 virtual const TargetLowering *getTargetLowering() const { return 0; }
124 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; }
125 virtual const TargetData *getTargetData() const { return 0; }
127 /// getMCAsmInfo - Return target specific asm information.
129 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
131 /// getSubtarget - This method returns a pointer to the specified type of
132 /// TargetSubtargetInfo. In debug builds, it verifies that the object being
133 /// returned is of the correct type.
134 template<typename STC> const STC &getSubtarget() const {
135 return *static_cast<const STC*>(getSubtargetImpl());
138 /// getRegisterInfo - If register information is available, return it. If
139 /// not, return null. This is kept separate from RegInfo until RegInfo has
140 /// details of graph coloring register allocation removed from it.
142 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
144 /// getIntrinsicInfo - If intrinsic information is available, return it. If
145 /// not, return null.
147 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
149 /// getJITInfo - If this target supports a JIT, return information for it,
150 /// otherwise return null.
152 virtual TargetJITInfo *getJITInfo() { return 0; }
154 /// getInstrItineraryData - Returns instruction itinerary data for the target
155 /// or specific subtarget.
157 virtual const InstrItineraryData *getInstrItineraryData() const {
161 /// getELFWriterInfo - If this target supports an ELF writer, return
162 /// information for it, otherwise return null.
164 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
166 /// hasMCRelaxAll - Check whether all machine code instructions should be
168 bool hasMCRelaxAll() const { return MCRelaxAll; }
170 /// setMCRelaxAll - Set whether all machine code instructions should be
172 void setMCRelaxAll(bool Value) { MCRelaxAll = Value; }
174 /// hasMCSaveTempLabels - Check whether temporary labels will be preserved
175 /// (i.e., not treated as temporary).
176 bool hasMCSaveTempLabels() const { return MCSaveTempLabels; }
178 /// setMCSaveTempLabels - Set whether temporary labels will be preserved
179 /// (i.e., not treated as temporary).
180 void setMCSaveTempLabels(bool Value) { MCSaveTempLabels = Value; }
182 /// hasMCNoExecStack - Check whether an executable stack is not needed.
183 bool hasMCNoExecStack() const { return MCNoExecStack; }
185 /// setMCNoExecStack - Set whether an executabel stack is not needed.
186 void setMCNoExecStack(bool Value) { MCNoExecStack = Value; }
188 /// hasMCUseLoc - Check whether we should use dwarf's .loc directive.
189 bool hasMCUseLoc() const { return MCUseLoc; }
191 /// setMCUseLoc - Set whether all we should use dwarf's .loc directive.
192 void setMCUseLoc(bool Value) { MCUseLoc = Value; }
194 /// hasMCUseCFI - Check whether we should use dwarf's .cfi_* directives.
195 bool hasMCUseCFI() const { return MCUseCFI; }
197 /// setMCUseCFI - Set whether all we should use dwarf's .cfi_* directives.
198 void setMCUseCFI(bool Value) { MCUseCFI = Value; }
200 /// hasMCUseDwarfDirectory - Check whether we should use .file directives with
201 /// explicit directories.
202 bool hasMCUseDwarfDirectory() const { return MCUseDwarfDirectory; }
204 /// setMCUseDwarfDirectory - Set whether all we should use .file directives
205 /// with explicit directories.
206 void setMCUseDwarfDirectory(bool Value) { MCUseDwarfDirectory = Value; }
208 /// getRelocationModel - Returns the code generation relocation model. The
209 /// choices are static, PIC, and dynamic-no-pic, and target default.
210 Reloc::Model getRelocationModel() const;
212 /// getCodeModel - Returns the code model. The choices are small, kernel,
213 /// medium, large, and target default.
214 CodeModel::Model getCodeModel() const;
216 /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
218 static bool getAsmVerbosityDefault();
220 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
222 static void setAsmVerbosityDefault(bool);
224 /// getDataSections - Return true if data objects should be emitted into their
225 /// own section, corresponds to -fdata-sections.
226 static bool getDataSections();
228 /// getFunctionSections - Return true if functions should be emitted into
229 /// their own section, corresponding to -ffunction-sections.
230 static bool getFunctionSections();
232 /// setDataSections - Set if the data are emit into separate sections.
233 static void setDataSections(bool);
235 /// setFunctionSections - Set if the functions are emit into separate
237 static void setFunctionSections(bool);
239 /// CodeGenFileType - These enums are meant to be passed into
240 /// addPassesToEmitFile to indicate what type of file to emit, and returned by
241 /// it to indicate what type of file could actually be made.
242 enum CodeGenFileType {
245 CGFT_Null // Do not emit any output.
248 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
249 /// on this target. User flag overrides.
250 virtual bool getEnableTailMergeDefault() const { return true; }
252 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
253 /// specified file emitted. Typically this will involve several steps of code
254 /// generation. This method should return true if emission of this file type
255 /// is not supported, or false on success.
256 virtual bool addPassesToEmitFile(PassManagerBase &,
257 formatted_raw_ostream &,
264 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
265 /// get machine code emitted. This uses a JITCodeEmitter object to handle
266 /// actually outputting the machine code and resolving things like the address
267 /// of functions. This method returns true if machine code emission is
270 virtual bool addPassesToEmitMachineCode(PassManagerBase &,
277 /// addPassesToEmitMC - Add passes to the specified pass manager to get
278 /// machine code emitted with the MCJIT. This method returns true if machine
279 /// code is not supported. It fills the MCContext Ctx pointer which can be
280 /// used to build custom MCStreamer.
282 virtual bool addPassesToEmitMC(PassManagerBase &,
291 /// LLVMTargetMachine - This class describes a target machine that is
292 /// implemented with the LLVM target-independent code generator.
294 class LLVMTargetMachine : public TargetMachine {
295 protected: // Can only create subclasses.
296 LLVMTargetMachine(const Target &T, StringRef TargetTriple,
297 StringRef CPU, StringRef FS,
298 Reloc::Model RM, CodeModel::Model CM);
301 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
302 /// both emitting to assembly files or machine code output.
304 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
305 bool DisableVerify, MCContext *&OutCtx);
308 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
309 /// specified file emitted. Typically this will involve several steps of code
310 /// generation. If OptLevel is None, the code generator should emit code as
311 /// fast as possible, though the generated code may be less efficient.
312 virtual bool addPassesToEmitFile(PassManagerBase &PM,
313 formatted_raw_ostream &Out,
314 CodeGenFileType FileType,
316 bool DisableVerify = true);
318 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
319 /// get machine code emitted. This uses a JITCodeEmitter object to handle
320 /// actually outputting the machine code and resolving things like the address
321 /// of functions. This method returns true if machine code emission is
324 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
327 bool DisableVerify = true);
329 /// addPassesToEmitMC - Add passes to the specified pass manager to get
330 /// machine code emitted with the MCJIT. This method returns true if machine
331 /// code is not supported. It fills the MCContext Ctx pointer which can be
332 /// used to build custom MCStreamer.
334 virtual bool addPassesToEmitMC(PassManagerBase &PM,
337 CodeGenOpt::Level OptLevel,
338 bool DisableVerify = true);
340 /// Target-Independent Code Generator Pass Configuration Options.
342 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
343 /// passes (which are run just before instruction selector).
344 virtual bool addPreISel(PassManagerBase &, CodeGenOpt::Level) {
348 /// addInstSelector - This method should install an instruction selector pass,
349 /// which converts from LLVM code to machine instructions.
350 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
354 /// addPreRegAlloc - This method may be implemented by targets that want to
355 /// run passes immediately before register allocation. This should return
356 /// true if -print-machineinstrs should print after these passes.
357 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
361 /// addPostRegAlloc - This method may be implemented by targets that want
362 /// to run passes after register allocation but before prolog-epilog
363 /// insertion. This should return true if -print-machineinstrs should print
364 /// after these passes.
365 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
369 /// addPreSched2 - This method may be implemented by targets that want to
370 /// run passes after prolog-epilog insertion and before the second instruction
371 /// scheduling pass. This should return true if -print-machineinstrs should
372 /// print after these passes.
373 virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
377 /// addPreEmitPass - This pass may be implemented by targets that want to run
378 /// passes immediately before machine code is emitted. This should return
379 /// true if -print-machineinstrs should print out the code after the passes.
380 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
385 /// addCodeEmitter - This pass should be overridden by the target to add a
386 /// code emitter, if supported. If this is not supported, 'true' should be
388 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
393 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
394 /// on this target. User flag overrides.
395 virtual bool getEnableTailMergeDefault() const { return true; }
398 } // End llvm namespace