1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file describes how to lower LLVM code to machine code. This has two
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
18 /// In addition it has a few other components, like information about FP
21 //===----------------------------------------------------------------------===//
23 #ifndef LLVM_TARGET_TARGETLOWERING_H
24 #define LLVM_TARGET_TARGETLOWERING_H
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/CodeGen/DAGCombine.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/IR/Attributes.h"
31 #include "llvm/IR/CallSite.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/IRBuilder.h"
34 #include "llvm/IR/InlineAsm.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/MC/MCRegisterInfo.h"
37 #include "llvm/Target/TargetCallingConv.h"
38 #include "llvm/Target/TargetMachine.h"
47 class FunctionLoweringInfo;
48 class ImmutableCallSite;
50 class MachineBasicBlock;
51 class MachineFunction;
53 class MachineJumpTableInfo;
59 template<typename T> class SmallVectorImpl;
61 class TargetRegisterClass;
62 class TargetLibraryInfo;
63 class TargetLoweringObjectFile;
68 None, // No preference
69 Source, // Follow source order.
70 RegPressure, // Scheduling for lowest register pressure.
71 Hybrid, // Scheduling for both latency and register pressure.
72 ILP, // Scheduling for ILP in low register pressure mode.
73 VLIW // Scheduling for VLIW targets.
77 /// This base class for TargetLowering contains the SelectionDAG-independent
78 /// parts that can be used from the rest of CodeGen.
79 class TargetLoweringBase {
80 TargetLoweringBase(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
81 void operator=(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
84 /// This enum indicates whether operations are valid for a target, and if not,
85 /// what action should be used to make them valid.
87 Legal, // The target natively supports this operation.
88 Promote, // This operation should be executed in a larger type.
89 Expand, // Try to expand this to other ops, otherwise use a libcall.
90 Custom // Use the LowerOperation hook to implement custom lowering.
93 /// This enum indicates whether a types are legal for a target, and if not,
94 /// what action should be used to make them valid.
95 enum LegalizeTypeAction {
96 TypeLegal, // The target natively supports this type.
97 TypePromoteInteger, // Replace this integer with a larger one.
98 TypeExpandInteger, // Split this integer into two of half the size.
99 TypeSoftenFloat, // Convert this float to a same size integer type.
100 TypeExpandFloat, // Split this float into two of half the size.
101 TypeScalarizeVector, // Replace this one-element vector with its element.
102 TypeSplitVector, // Split this vector into two of half the size.
103 TypeWidenVector // This vector should be widened into a larger vector.
106 /// LegalizeKind holds the legalization kind that needs to happen to EVT
107 /// in order to type-legalize it.
108 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
110 /// Enum that describes how the target represents true/false values.
111 enum BooleanContent {
112 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
113 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
114 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
117 /// Enum that describes what type of support for selects the target has.
118 enum SelectSupportKind {
119 ScalarValSelect, // The target supports scalar selects (ex: cmov).
120 ScalarCondVectorVal, // The target supports selects with a scalar condition
121 // and vector values (ex: cmov).
122 VectorMaskSelect // The target supports vector selects with a vector
123 // mask (ex: x86 blends).
126 static ISD::NodeType getExtendForContent(BooleanContent Content) {
128 case UndefinedBooleanContent:
129 // Extend by adding rubbish bits.
130 return ISD::ANY_EXTEND;
131 case ZeroOrOneBooleanContent:
132 // Extend by adding zero bits.
133 return ISD::ZERO_EXTEND;
134 case ZeroOrNegativeOneBooleanContent:
135 // Extend by copying the sign bit.
136 return ISD::SIGN_EXTEND;
138 llvm_unreachable("Invalid content kind");
141 /// NOTE: The TargetMachine owns TLOF.
142 explicit TargetLoweringBase(const TargetMachine &TM);
143 virtual ~TargetLoweringBase() {}
146 /// \brief Initialize all of the actions to default values.
150 const TargetMachine &getTargetMachine() const { return TM; }
151 const DataLayout *getDataLayout() const { return DL; }
153 bool isBigEndian() const { return !IsLittleEndian; }
154 bool isLittleEndian() const { return IsLittleEndian; }
156 /// Return the pointer type for the given address space, defaults to
157 /// the pointer type from the data layout.
158 /// FIXME: The default needs to be removed once all the code is updated.
159 virtual MVT getPointerTy(uint32_t /*AS*/ = 0) const;
160 unsigned getPointerSizeInBits(uint32_t AS = 0) const;
161 unsigned getPointerTypeSizeInBits(Type *Ty) const;
162 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const;
164 EVT getShiftAmountTy(EVT LHSTy) const;
166 /// Returns the type to be used for the index operand of:
167 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
168 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
169 virtual MVT getVectorIdxTy() const {
170 return getPointerTy();
173 /// Return true if the select operation is expensive for this target.
174 bool isSelectExpensive() const { return SelectIsExpensive; }
176 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
180 /// Return true if multiple condition registers are available.
181 bool hasMultipleConditionRegisters() const {
182 return HasMultipleConditionRegisters;
185 /// Return true if the target has BitExtract instructions.
186 bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
188 /// Return the preferred vector type legalization action.
189 virtual TargetLoweringBase::LegalizeTypeAction
190 getPreferredVectorAction(EVT VT) const {
191 // The default action for one element vectors is to scalarize
192 if (VT.getVectorNumElements() == 1)
193 return TypeScalarizeVector;
194 // The default action for other vectors is to promote
195 return TypePromoteInteger;
198 // There are two general methods for expanding a BUILD_VECTOR node:
199 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
201 // 2. Build the vector on the stack and then load it.
202 // If this function returns true, then method (1) will be used, subject to
203 // the constraint that all of the necessary shuffles are legal (as determined
204 // by isShuffleMaskLegal). If this function returns false, then method (2) is
205 // always used. The vector type, and the number of defined values, are
208 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
209 unsigned DefinedValues) const {
210 return DefinedValues < 3;
213 /// Return true if integer divide is usually cheaper than a sequence of
214 /// several shifts, adds, and multiplies for this target.
215 bool isIntDivCheap() const { return IntDivIsCheap; }
217 /// Return true if sqrt(x) is as cheap or cheaper than 1 / rsqrt(x)
218 bool isFsqrtCheap() const {
222 /// Returns true if target has indicated at least one type should be bypassed.
223 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
225 /// Returns map of slow types for division or remainder with corresponding
227 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
228 return BypassSlowDivWidths;
231 /// Return true if pow2 sdiv is cheaper than a chain of sra/srl/add/sra.
232 bool isPow2SDivCheap() const { return Pow2SDivIsCheap; }
234 /// Return true if Flow Control is an expensive operation that should be
236 bool isJumpExpensive() const { return JumpIsExpensive; }
238 /// Return true if selects are only cheaper than branches if the branch is
239 /// unlikely to be predicted right.
240 bool isPredictableSelectExpensive() const {
241 return PredictableSelectIsExpensive;
244 /// isLoadBitCastBeneficial() - Return true if the following transform
246 /// fold (conv (load x)) -> (load (conv*)x)
247 /// On architectures that don't natively support some vector loads efficiently,
248 /// casting the load to a smaller vector of larger types and loading
249 /// is more efficient, however, this can be undone by optimizations in
251 virtual bool isLoadBitCastBeneficial(EVT /* Load */, EVT /* Bitcast */) const {
255 /// \brief Return true if it is cheap to speculate a call to intrinsic cttz.
256 virtual bool isCheapToSpeculateCttz() const {
260 /// \brief Return true if it is cheap to speculate a call to intrinsic ctlz.
261 virtual bool isCheapToSpeculateCtlz() const {
265 /// \brief Return if the target supports combining a
268 /// %andResult = and %val1, #imm-with-one-bit-set;
269 /// %icmpResult = icmp %andResult, 0
270 /// br i1 %icmpResult, label %dest1, label %dest2
272 /// into a single machine instruction of a form like:
274 /// brOnBitSet %register, #bitNumber, dest
276 bool isMaskAndBranchFoldingLegal() const {
277 return MaskAndBranchFoldingIsLegal;
280 /// \brief Return true if the target wants to use the optimization that
281 /// turns ext(promotableInst1(...(promotableInstN(load)))) into
282 /// promotedInst1(...(promotedInstN(ext(load)))).
283 bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
285 /// Return true if the target can combine store(extractelement VectorTy,
287 /// \p Cost[out] gives the cost of that transformation when this is true.
288 virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
289 unsigned &Cost) const {
293 /// Return true if target supports floating point exceptions.
294 bool hasFloatingPointExceptions() const {
295 return HasFloatingPointExceptions;
298 /// Return true if target always beneficiates from combining into FMA for a
299 /// given value type. This must typically return false on targets where FMA
300 /// takes more cycles to execute than FADD.
301 virtual bool enableAggressiveFMAFusion(EVT VT) const {
305 /// Return the ValueType of the result of SETCC operations.
306 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
308 /// Return the ValueType for comparison libcalls. Comparions libcalls include
309 /// floating point comparion calls, and Ordered/Unordered check calls on
310 /// floating point numbers.
312 MVT::SimpleValueType getCmpLibcallReturnType() const;
314 /// For targets without i1 registers, this gives the nature of the high-bits
315 /// of boolean values held in types wider than i1.
317 /// "Boolean values" are special true/false values produced by nodes like
318 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
319 /// Not to be confused with general values promoted from i1. Some cpus
320 /// distinguish between vectors of boolean and scalars; the isVec parameter
321 /// selects between the two kinds. For example on X86 a scalar boolean should
322 /// be zero extended from i1, while the elements of a vector of booleans
323 /// should be sign extended from i1.
325 /// Some cpus also treat floating point types the same way as they treat
326 /// vectors instead of the way they treat scalars.
327 BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
329 return BooleanVectorContents;
330 return isFloat ? BooleanFloatContents : BooleanContents;
333 BooleanContent getBooleanContents(EVT Type) const {
334 return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
337 /// Return target scheduling preference.
338 Sched::Preference getSchedulingPreference() const {
339 return SchedPreferenceInfo;
342 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
343 /// for different nodes. This function returns the preference (or none) for
345 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
349 /// Return the register class that should be used for the specified value
351 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
352 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
353 assert(RC && "This value type is not natively supported!");
357 /// Return the 'representative' register class for the specified value
360 /// The 'representative' register class is the largest legal super-reg
361 /// register class for the register class of the value type. For example, on
362 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
363 /// register class is GR64 on x86_64.
364 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
365 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
369 /// Return the cost of the 'representative' register class for the specified
371 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
372 return RepRegClassCostForVT[VT.SimpleTy];
375 /// Return true if the target has native support for the specified value type.
376 /// This means that it has a register that directly holds it without
377 /// promotions or expansions.
378 bool isTypeLegal(EVT VT) const {
379 assert(!VT.isSimple() ||
380 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
381 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
384 class ValueTypeActionImpl {
385 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
386 /// that indicates how instruction selection should deal with the type.
387 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
390 ValueTypeActionImpl() {
391 std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions), 0);
394 LegalizeTypeAction getTypeAction(MVT VT) const {
395 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy];
398 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
399 unsigned I = VT.SimpleTy;
400 ValueTypeActions[I] = Action;
404 const ValueTypeActionImpl &getValueTypeActions() const {
405 return ValueTypeActions;
408 /// Return how we should legalize values of this type, either it is already
409 /// legal (return 'Legal') or we need to promote it to a larger type (return
410 /// 'Promote'), or we need to expand it into multiple registers of smaller
411 /// integer type (return 'Expand'). 'Custom' is not an option.
412 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
413 return getTypeConversion(Context, VT).first;
415 LegalizeTypeAction getTypeAction(MVT VT) const {
416 return ValueTypeActions.getTypeAction(VT);
419 /// For types supported by the target, this is an identity function. For
420 /// types that must be promoted to larger types, this returns the larger type
421 /// to promote to. For integer types that are larger than the largest integer
422 /// register, this contains one step in the expansion to get to the smaller
423 /// register. For illegal floating point types, this returns the integer type
425 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
426 return getTypeConversion(Context, VT).second;
429 /// For types supported by the target, this is an identity function. For
430 /// types that must be expanded (i.e. integer types that are larger than the
431 /// largest integer register or illegal floating point types), this returns
432 /// the largest legal type it will be expanded to.
433 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
434 assert(!VT.isVector());
436 switch (getTypeAction(Context, VT)) {
439 case TypeExpandInteger:
440 VT = getTypeToTransformTo(Context, VT);
443 llvm_unreachable("Type is not legal nor is it to be expanded!");
448 /// Vector types are broken down into some number of legal first class types.
449 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
450 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
451 /// turns into 4 EVT::i32 values with both PPC and X86.
453 /// This method returns the number of registers needed, and the VT for each
454 /// register. It also returns the VT and quantity of the intermediate values
455 /// before they are promoted/expanded.
456 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
458 unsigned &NumIntermediates,
459 MVT &RegisterVT) const;
461 struct IntrinsicInfo {
462 unsigned opc; // target opcode
463 EVT memVT; // memory VT
464 const Value* ptrVal; // value representing memory location
465 int offset; // offset off of ptrVal
466 unsigned size; // the size of the memory location
467 // (taken from memVT if zero)
468 unsigned align; // alignment
469 bool vol; // is volatile?
470 bool readMem; // reads memory?
471 bool writeMem; // writes memory?
473 IntrinsicInfo() : opc(0), ptrVal(nullptr), offset(0), size(0), align(1),
474 vol(false), readMem(false), writeMem(false) {}
477 /// Given an intrinsic, checks if on the target the intrinsic will need to map
478 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
479 /// true and store the intrinsic information into the IntrinsicInfo that was
480 /// passed to the function.
481 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
482 unsigned /*Intrinsic*/) const {
486 /// Returns true if the target can instruction select the specified FP
487 /// immediate natively. If false, the legalizer will materialize the FP
488 /// immediate as a load from a constant pool.
489 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
493 /// Targets can use this to indicate that they only support *some*
494 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
495 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
497 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
502 /// Returns true if the operation can trap for the value type.
504 /// VT must be a legal type. By default, we optimistically assume most
505 /// operations don't trap except for divide and remainder.
506 virtual bool canOpTrap(unsigned Op, EVT VT) const;
508 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
509 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
510 /// a VAND with a constant pool entry.
511 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
516 /// Return how this operation should be treated: either it is legal, needs to
517 /// be promoted to a larger size, needs to be expanded to some other code
518 /// sequence, or the target has a custom expander for it.
519 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
520 if (VT.isExtended()) return Expand;
521 // If a target-specific SDNode requires legalization, require the target
522 // to provide custom legalization for it.
523 if (Op > array_lengthof(OpActions[0])) return Custom;
524 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
525 return (LegalizeAction)OpActions[I][Op];
528 /// Return true if the specified operation is legal on this target or can be
529 /// made legal with custom lowering. This is used to help guide high-level
530 /// lowering decisions.
531 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
532 return (VT == MVT::Other || isTypeLegal(VT)) &&
533 (getOperationAction(Op, VT) == Legal ||
534 getOperationAction(Op, VT) == Custom);
537 /// Return true if the specified operation is legal on this target or can be
538 /// made legal using promotion. This is used to help guide high-level lowering
540 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
541 return (VT == MVT::Other || isTypeLegal(VT)) &&
542 (getOperationAction(Op, VT) == Legal ||
543 getOperationAction(Op, VT) == Promote);
546 /// Return true if the specified operation is illegal on this target or
547 /// unlikely to be made legal with custom lowering. This is used to help guide
548 /// high-level lowering decisions.
549 bool isOperationExpand(unsigned Op, EVT VT) const {
550 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
553 /// Return true if the specified operation is legal on this target.
554 bool isOperationLegal(unsigned Op, EVT VT) const {
555 return (VT == MVT::Other || isTypeLegal(VT)) &&
556 getOperationAction(Op, VT) == Legal;
559 /// Return how this load with extension should be treated: either it is legal,
560 /// needs to be promoted to a larger size, needs to be expanded to some other
561 /// code sequence, or the target has a custom expander for it.
562 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const {
563 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
564 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
565 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
566 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
567 MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
568 return (LegalizeAction)LoadExtActions[ValI][MemI][ExtType];
571 /// Return true if the specified load with extension is legal on this target.
572 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
573 return ValVT.isSimple() && MemVT.isSimple() &&
574 getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
577 /// Return how this store with truncation should be treated: either it is
578 /// legal, needs to be promoted to a larger size, needs to be expanded to some
579 /// other code sequence, or the target has a custom expander for it.
580 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
581 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
582 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
583 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
584 assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
585 "Table isn't big enough!");
586 return (LegalizeAction)TruncStoreActions[ValI][MemI];
589 /// Return true if the specified store with truncation is legal on this
591 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
592 return isTypeLegal(ValVT) && MemVT.isSimple() &&
593 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
596 /// Return how the indexed load should be treated: either it is legal, needs
597 /// to be promoted to a larger size, needs to be expanded to some other code
598 /// sequence, or the target has a custom expander for it.
600 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
601 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
602 "Table isn't big enough!");
603 unsigned Ty = (unsigned)VT.SimpleTy;
604 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
607 /// Return true if the specified indexed load is legal on this target.
608 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
609 return VT.isSimple() &&
610 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
611 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
614 /// Return how the indexed store should be treated: either it is legal, needs
615 /// to be promoted to a larger size, needs to be expanded to some other code
616 /// sequence, or the target has a custom expander for it.
618 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
619 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
620 "Table isn't big enough!");
621 unsigned Ty = (unsigned)VT.SimpleTy;
622 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
625 /// Return true if the specified indexed load is legal on this target.
626 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
627 return VT.isSimple() &&
628 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
629 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
632 /// Return how the condition code should be treated: either it is legal, needs
633 /// to be expanded to some other code sequence, or the target has a custom
636 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
637 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
638 ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) &&
639 "Table isn't big enough!");
640 // See setCondCodeAction for how this is encoded.
641 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
642 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4];
643 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3);
644 assert(Action != Promote && "Can't promote condition code!");
648 /// Return true if the specified condition code is legal on this target.
649 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
651 getCondCodeAction(CC, VT) == Legal ||
652 getCondCodeAction(CC, VT) == Custom;
656 /// If the action for this operation is to promote, this method returns the
657 /// ValueType to promote to.
658 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
659 assert(getOperationAction(Op, VT) == Promote &&
660 "This operation isn't promoted!");
662 // See if this has an explicit type specified.
663 std::map<std::pair<unsigned, MVT::SimpleValueType>,
664 MVT::SimpleValueType>::const_iterator PTTI =
665 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
666 if (PTTI != PromoteToType.end()) return PTTI->second;
668 assert((VT.isInteger() || VT.isFloatingPoint()) &&
669 "Cannot autopromote this type, add it with AddPromotedToType.");
673 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
674 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
675 "Didn't find type to promote to!");
676 } while (!isTypeLegal(NVT) ||
677 getOperationAction(Op, NVT) == Promote);
681 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
682 /// operations except for the pointer size. If AllowUnknown is true, this
683 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
684 /// otherwise it will assert.
685 EVT getValueType(Type *Ty, bool AllowUnknown = false) const {
686 // Lower scalar pointers to native pointer types.
687 if (PointerType *PTy = dyn_cast<PointerType>(Ty))
688 return getPointerTy(PTy->getAddressSpace());
690 if (Ty->isVectorTy()) {
691 VectorType *VTy = cast<VectorType>(Ty);
692 Type *Elm = VTy->getElementType();
693 // Lower vectors of pointers to native pointer types.
694 if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
695 EVT PointerTy(getPointerTy(PT->getAddressSpace()));
696 Elm = PointerTy.getTypeForEVT(Ty->getContext());
699 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
700 VTy->getNumElements());
702 return EVT::getEVT(Ty, AllowUnknown);
705 /// Return the MVT corresponding to this LLVM type. See getValueType.
706 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const {
707 return getValueType(Ty, AllowUnknown).getSimpleVT();
710 /// Return the desired alignment for ByVal or InAlloca aggregate function
711 /// arguments in the caller parameter area. This is the actual alignment, not
713 virtual unsigned getByValTypeAlignment(Type *Ty) const;
715 /// Return the type of registers that this ValueType will eventually require.
716 MVT getRegisterType(MVT VT) const {
717 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
718 return RegisterTypeForVT[VT.SimpleTy];
721 /// Return the type of registers that this ValueType will eventually require.
722 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
724 assert((unsigned)VT.getSimpleVT().SimpleTy <
725 array_lengthof(RegisterTypeForVT));
726 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
731 unsigned NumIntermediates;
732 (void)getVectorTypeBreakdown(Context, VT, VT1,
733 NumIntermediates, RegisterVT);
736 if (VT.isInteger()) {
737 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
739 llvm_unreachable("Unsupported extended type!");
742 /// Return the number of registers that this ValueType will eventually
745 /// This is one for any types promoted to live in larger registers, but may be
746 /// more than one for types (like i64) that are split into pieces. For types
747 /// like i140, which are first promoted then expanded, it is the number of
748 /// registers needed to hold all the bits of the original type. For an i140
749 /// on a 32 bit machine this means 5 registers.
750 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
752 assert((unsigned)VT.getSimpleVT().SimpleTy <
753 array_lengthof(NumRegistersForVT));
754 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
759 unsigned NumIntermediates;
760 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
762 if (VT.isInteger()) {
763 unsigned BitWidth = VT.getSizeInBits();
764 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
765 return (BitWidth + RegWidth - 1) / RegWidth;
767 llvm_unreachable("Unsupported extended type!");
770 /// If true, then instruction selection should seek to shrink the FP constant
771 /// of the specified type to a smaller type in order to save space and / or
773 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
775 // Return true if it is profitable to reduce the given load node to a smaller
778 // e.g. (i16 (trunc (i32 (load x))) -> i16 load x should be performed
779 virtual bool shouldReduceLoadWidth(SDNode *Load,
780 ISD::LoadExtType ExtTy,
785 /// When splitting a value of the specified type into parts, does the Lo
786 /// or Hi part come first? This usually follows the endianness, except
787 /// for ppcf128, where the Hi part always comes first.
788 bool hasBigEndianPartOrdering(EVT VT) const {
789 return isBigEndian() || VT == MVT::ppcf128;
792 /// If true, the target has custom DAG combine transformations that it can
793 /// perform for the specified node.
794 bool hasTargetDAGCombine(ISD::NodeType NT) const {
795 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
796 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
799 /// \brief Get maximum # of store operations permitted for llvm.memset
801 /// This function returns the maximum number of store operations permitted
802 /// to replace a call to llvm.memset. The value is set by the target at the
803 /// performance threshold for such a replacement. If OptSize is true,
804 /// return the limit for functions that have OptSize attribute.
805 unsigned getMaxStoresPerMemset(bool OptSize) const {
806 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
809 /// \brief Get maximum # of store operations permitted for llvm.memcpy
811 /// This function returns the maximum number of store operations permitted
812 /// to replace a call to llvm.memcpy. The value is set by the target at the
813 /// performance threshold for such a replacement. If OptSize is true,
814 /// return the limit for functions that have OptSize attribute.
815 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
816 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
819 /// \brief Get maximum # of store operations permitted for llvm.memmove
821 /// This function returns the maximum number of store operations permitted
822 /// to replace a call to llvm.memmove. The value is set by the target at the
823 /// performance threshold for such a replacement. If OptSize is true,
824 /// return the limit for functions that have OptSize attribute.
825 unsigned getMaxStoresPerMemmove(bool OptSize) const {
826 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
829 /// \brief Determine if the target supports unaligned memory accesses.
831 /// This function returns true if the target allows unaligned memory accesses
832 /// of the specified type in the given address space. If true, it also returns
833 /// whether the unaligned memory access is "fast" in the last argument by
834 /// reference. This is used, for example, in situations where an array
835 /// copy/move/set is converted to a sequence of store operations. Its use
836 /// helps to ensure that such replacements don't generate code that causes an
837 /// alignment error (trap) on the target machine.
838 virtual bool allowsMisalignedMemoryAccesses(EVT,
839 unsigned AddrSpace = 0,
841 bool * /*Fast*/ = nullptr) const {
845 /// Returns the target specific optimal type for load and store operations as
846 /// a result of memset, memcpy, and memmove lowering.
848 /// If DstAlign is zero that means it's safe to destination alignment can
849 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
850 /// a need to check it against alignment requirement, probably because the
851 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
852 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
853 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
854 /// does not need to be loaded. It returns EVT::Other if the type should be
855 /// determined using generic target-independent logic.
856 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
857 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
860 bool /*MemcpyStrSrc*/,
861 MachineFunction &/*MF*/) const {
865 /// Returns true if it's safe to use load / store of the specified type to
866 /// expand memcpy / memset inline.
868 /// This is mostly true for all types except for some special cases. For
869 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
870 /// fstpl which also does type conversion. Note the specified type doesn't
871 /// have to be legal as the hook is used before type legalization.
872 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
874 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
875 bool usesUnderscoreSetJmp() const {
876 return UseUnderscoreSetJmp;
879 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
880 bool usesUnderscoreLongJmp() const {
881 return UseUnderscoreLongJmp;
884 /// Return integer threshold on number of blocks to use jump tables rather
885 /// than if sequence.
886 int getMinimumJumpTableEntries() const {
887 return MinimumJumpTableEntries;
890 /// If a physical register, this specifies the register that
891 /// llvm.savestack/llvm.restorestack should save and restore.
892 unsigned getStackPointerRegisterToSaveRestore() const {
893 return StackPointerRegisterToSaveRestore;
896 /// If a physical register, this returns the register that receives the
897 /// exception address on entry to a landing pad.
898 unsigned getExceptionPointerRegister() const {
899 return ExceptionPointerRegister;
902 /// If a physical register, this returns the register that receives the
903 /// exception typeid on entry to a landing pad.
904 unsigned getExceptionSelectorRegister() const {
905 return ExceptionSelectorRegister;
908 /// Returns the target's jmp_buf size in bytes (if never set, the default is
910 unsigned getJumpBufSize() const {
914 /// Returns the target's jmp_buf alignment in bytes (if never set, the default
916 unsigned getJumpBufAlignment() const {
917 return JumpBufAlignment;
920 /// Return the minimum stack alignment of an argument.
921 unsigned getMinStackArgumentAlignment() const {
922 return MinStackArgumentAlignment;
925 /// Return the minimum function alignment.
926 unsigned getMinFunctionAlignment() const {
927 return MinFunctionAlignment;
930 /// Return the preferred function alignment.
931 unsigned getPrefFunctionAlignment() const {
932 return PrefFunctionAlignment;
935 /// Return the preferred loop alignment.
936 virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
937 return PrefLoopAlignment;
940 /// Return whether the DAG builder should automatically insert fences and
941 /// reduce ordering for atomics.
942 bool getInsertFencesForAtomic() const {
943 return InsertFencesForAtomic;
946 /// Return true if the target stores stack protector cookies at a fixed offset
947 /// in some non-standard address space, and populates the address space and
948 /// offset as appropriate.
949 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
950 unsigned &/*Offset*/) const {
954 /// Returns the maximal possible offset which can be used for loads / stores
956 virtual unsigned getMaximalGlobalOffset() const {
960 /// Returns true if a cast between SrcAS and DestAS is a noop.
961 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
965 //===--------------------------------------------------------------------===//
966 /// \name Helpers for TargetTransformInfo implementations
969 /// Get the ISD node that corresponds to the Instruction class opcode.
970 int InstructionOpcodeToISD(unsigned Opcode) const;
972 /// Estimate the cost of type-legalization and the legalized type.
973 std::pair<unsigned, MVT> getTypeLegalizationCost(Type *Ty) const;
977 //===--------------------------------------------------------------------===//
978 /// \name Helpers for atomic expansion.
981 /// True if AtomicExpandPass should use emitLoadLinked/emitStoreConditional
982 /// and expand AtomicCmpXchgInst.
983 virtual bool hasLoadLinkedStoreConditional() const { return false; }
985 /// Perform a load-linked operation on Addr, returning a "Value *" with the
986 /// corresponding pointee type. This may entail some non-trivial operations to
987 /// truncate or reconstruct types that will be illegal in the backend. See
988 /// ARMISelLowering for an example implementation.
989 virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
990 AtomicOrdering Ord) const {
991 llvm_unreachable("Load linked unimplemented on this target");
994 /// Perform a store-conditional operation to Addr. Return the status of the
995 /// store. This should be 0 if the store succeeded, non-zero otherwise.
996 virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
997 Value *Addr, AtomicOrdering Ord) const {
998 llvm_unreachable("Store conditional unimplemented on this target");
1001 /// Inserts in the IR a target-specific intrinsic specifying a fence.
1002 /// It is called by AtomicExpandPass before expanding an
1003 /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad.
1004 /// RMW and CmpXchg set both IsStore and IsLoad to true.
1005 /// This function should either return a nullptr, or a pointer to an IR-level
1006 /// Instruction*. Even complex fence sequences can be represented by a
1007 /// single Instruction* through an intrinsic to be lowered later.
1008 /// Backends with !getInsertFencesForAtomic() should keep a no-op here.
1009 /// Backends should override this method to produce target-specific intrinsic
1010 /// for their fences.
1011 /// FIXME: Please note that the default implementation here in terms of
1012 /// IR-level fences exists for historical/compatibility reasons and is
1013 /// *unsound* ! Fences cannot, in general, be used to restore sequential
1014 /// consistency. For example, consider the following example:
1015 /// atomic<int> x = y = 0;
1016 /// int r1, r2, r3, r4;
1027 /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1028 /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1029 /// IR-level fences can prevent it.
1031 virtual Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
1032 bool IsStore, bool IsLoad) const {
1033 if (!getInsertFencesForAtomic())
1036 if (isAtLeastRelease(Ord) && IsStore)
1037 return Builder.CreateFence(Ord);
1042 virtual Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
1043 bool IsStore, bool IsLoad) const {
1044 if (!getInsertFencesForAtomic())
1047 if (isAtLeastAcquire(Ord))
1048 return Builder.CreateFence(Ord);
1054 /// Returns true if the given (atomic) store should be expanded by the
1055 /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1056 virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1060 /// Returns true if the given (atomic) load should be expanded by the
1061 /// IR-level AtomicExpand pass into a load-linked instruction
1062 /// (through emitLoadLinked()).
1063 virtual bool shouldExpandAtomicLoadInIR(LoadInst *LI) const { return false; }
1065 /// Returns true if the given AtomicRMW should be expanded by the
1066 /// IR-level AtomicExpand pass into a loop using LoadLinked/StoreConditional.
1067 virtual bool shouldExpandAtomicRMWInIR(AtomicRMWInst *RMWI) const {
1071 /// On some platforms, an AtomicRMW that never actually modifies the value
1072 /// (such as fetch_add of 0) can be turned into a fence followed by an
1073 /// atomic load. This may sound useless, but it makes it possible for the
1074 /// processor to keep the cacheline shared, dramatically improving
1075 /// performance. And such idempotent RMWs are useful for implementing some
1076 /// kinds of locks, see for example (justification + benchmarks):
1077 /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1078 /// This method tries doing that transformation, returning the atomic load if
1079 /// it succeeds, and nullptr otherwise.
1080 /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1081 /// another round of expansion.
1082 virtual LoadInst *lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
1085 //===--------------------------------------------------------------------===//
1086 // TargetLowering Configuration Methods - These methods should be invoked by
1087 // the derived class constructor to configure this object for the target.
1090 /// Specify how the target extends the result of integer and floating point
1091 /// boolean values from i1 to a wider type. See getBooleanContents.
1092 void setBooleanContents(BooleanContent Ty) {
1093 BooleanContents = Ty;
1094 BooleanFloatContents = Ty;
1097 /// Specify how the target extends the result of integer and floating point
1098 /// boolean values from i1 to a wider type. See getBooleanContents.
1099 void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
1100 BooleanContents = IntTy;
1101 BooleanFloatContents = FloatTy;
1104 /// Specify how the target extends the result of a vector boolean value from a
1105 /// vector of i1 to a wider type. See getBooleanContents.
1106 void setBooleanVectorContents(BooleanContent Ty) {
1107 BooleanVectorContents = Ty;
1110 /// Specify the target scheduling preference.
1111 void setSchedulingPreference(Sched::Preference Pref) {
1112 SchedPreferenceInfo = Pref;
1115 /// Indicate whether this target prefers to use _setjmp to implement
1116 /// llvm.setjmp or the version without _. Defaults to false.
1117 void setUseUnderscoreSetJmp(bool Val) {
1118 UseUnderscoreSetJmp = Val;
1121 /// Indicate whether this target prefers to use _longjmp to implement
1122 /// llvm.longjmp or the version without _. Defaults to false.
1123 void setUseUnderscoreLongJmp(bool Val) {
1124 UseUnderscoreLongJmp = Val;
1127 /// Indicate the number of blocks to generate jump tables rather than if
1129 void setMinimumJumpTableEntries(int Val) {
1130 MinimumJumpTableEntries = Val;
1133 /// If set to a physical register, this specifies the register that
1134 /// llvm.savestack/llvm.restorestack should save and restore.
1135 void setStackPointerRegisterToSaveRestore(unsigned R) {
1136 StackPointerRegisterToSaveRestore = R;
1139 /// If set to a physical register, this sets the register that receives the
1140 /// exception address on entry to a landing pad.
1141 void setExceptionPointerRegister(unsigned R) {
1142 ExceptionPointerRegister = R;
1145 /// If set to a physical register, this sets the register that receives the
1146 /// exception typeid on entry to a landing pad.
1147 void setExceptionSelectorRegister(unsigned R) {
1148 ExceptionSelectorRegister = R;
1151 /// Tells the code generator not to expand operations into sequences that use
1152 /// the select operations if possible.
1153 void setSelectIsExpensive(bool isExpensive = true) {
1154 SelectIsExpensive = isExpensive;
1157 /// Tells the code generator that the target has multiple (allocatable)
1158 /// condition registers that can be used to store the results of comparisons
1159 /// for use by selects and conditional branches. With multiple condition
1160 /// registers, the code generator will not aggressively sink comparisons into
1161 /// the blocks of their users.
1162 void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1163 HasMultipleConditionRegisters = hasManyRegs;
1166 /// Tells the code generator that the target has BitExtract instructions.
1167 /// The code generator will aggressively sink "shift"s into the blocks of
1168 /// their users if the users will generate "and" instructions which can be
1169 /// combined with "shift" to BitExtract instructions.
1170 void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1171 HasExtractBitsInsn = hasExtractInsn;
1174 /// Tells the code generator not to expand sequence of operations into a
1175 /// separate sequences that increases the amount of flow control.
1176 void setJumpIsExpensive(bool isExpensive = true) {
1177 JumpIsExpensive = isExpensive;
1180 /// Tells the code generator that integer divide is expensive, and if
1181 /// possible, should be replaced by an alternate sequence of instructions not
1182 /// containing an integer divide.
1183 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
1185 /// Tells the code generator that fsqrt is cheap, and should not be replaced
1186 /// with an alternative sequence of instructions.
1187 void setFsqrtIsCheap(bool isCheap = true) { FsqrtIsCheap = isCheap; }
1189 /// Tells the code generator that this target supports floating point
1190 /// exceptions and cares about preserving floating point exception behavior.
1191 void setHasFloatingPointExceptions(bool FPExceptions = true) {
1192 HasFloatingPointExceptions = FPExceptions;
1195 /// Tells the code generator which bitwidths to bypass.
1196 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1197 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1200 /// Tells the code generator that it shouldn't generate sra/srl/add/sra for a
1201 /// signed divide by power of two; let the target handle it.
1202 void setPow2SDivIsCheap(bool isCheap = true) { Pow2SDivIsCheap = isCheap; }
1204 /// Add the specified register class as an available regclass for the
1205 /// specified value type. This indicates the selector can handle values of
1206 /// that class natively.
1207 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1208 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1209 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1210 RegClassForVT[VT.SimpleTy] = RC;
1213 /// Remove all register classes.
1214 void clearRegisterClasses() {
1215 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
1217 AvailableRegClasses.clear();
1220 /// \brief Remove all operation actions.
1221 void clearOperationActions() {
1224 /// Return the largest legal super-reg register class of the register class
1225 /// for the specified type and its associated "cost".
1226 virtual std::pair<const TargetRegisterClass*, uint8_t>
1227 findRepresentativeClass(MVT VT) const;
1229 /// Once all of the register classes are added, this allows us to compute
1230 /// derived properties we expose.
1231 void computeRegisterProperties();
1233 /// Indicate that the specified operation does not work with the specified
1234 /// type and indicate what to do about it.
1235 void setOperationAction(unsigned Op, MVT VT,
1236 LegalizeAction Action) {
1237 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1238 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1241 /// Indicate that the specified load with extension does not work with the
1242 /// specified type and indicate what to do about it.
1243 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1244 LegalizeAction Action) {
1245 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1246 MemVT.isValid() && "Table isn't big enough!");
1247 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy][ExtType] = (uint8_t)Action;
1250 /// Indicate that the specified truncating store does not work with the
1251 /// specified type and indicate what to do about it.
1252 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1253 LegalizeAction Action) {
1254 assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1255 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1258 /// Indicate that the specified indexed load does or does not work with the
1259 /// specified type and indicate what to do abort it.
1261 /// NOTE: All indexed mode loads are initialized to Expand in
1262 /// TargetLowering.cpp
1263 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1264 LegalizeAction Action) {
1265 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1266 (unsigned)Action < 0xf && "Table isn't big enough!");
1267 // Load action are kept in the upper half.
1268 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1269 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1272 /// Indicate that the specified indexed store does or does not work with the
1273 /// specified type and indicate what to do about it.
1275 /// NOTE: All indexed mode stores are initialized to Expand in
1276 /// TargetLowering.cpp
1277 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1278 LegalizeAction Action) {
1279 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1280 (unsigned)Action < 0xf && "Table isn't big enough!");
1281 // Store action are kept in the lower half.
1282 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1283 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1286 /// Indicate that the specified condition code is or isn't supported on the
1287 /// target and indicate what to do about it.
1288 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1289 LegalizeAction Action) {
1290 assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1291 "Table isn't big enough!");
1292 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit
1293 /// value and the upper 27 bits index into the second dimension of the array
1294 /// to select what 32-bit value to use.
1295 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
1296 CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
1297 CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
1300 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1301 /// to trying a larger integer/fp until it can find one that works. If that
1302 /// default is insufficient, this method can be used by the target to override
1304 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1305 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1308 /// Targets should invoke this method for each target independent node that
1309 /// they want to provide a custom DAG combiner for by implementing the
1310 /// PerformDAGCombine virtual method.
1311 void setTargetDAGCombine(ISD::NodeType NT) {
1312 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1313 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1316 /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1317 void setJumpBufSize(unsigned Size) {
1321 /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1323 void setJumpBufAlignment(unsigned Align) {
1324 JumpBufAlignment = Align;
1327 /// Set the target's minimum function alignment (in log2(bytes))
1328 void setMinFunctionAlignment(unsigned Align) {
1329 MinFunctionAlignment = Align;
1332 /// Set the target's preferred function alignment. This should be set if
1333 /// there is a performance benefit to higher-than-minimum alignment (in
1335 void setPrefFunctionAlignment(unsigned Align) {
1336 PrefFunctionAlignment = Align;
1339 /// Set the target's preferred loop alignment. Default alignment is zero, it
1340 /// means the target does not care about loop alignment. The alignment is
1341 /// specified in log2(bytes). The target may also override
1342 /// getPrefLoopAlignment to provide per-loop values.
1343 void setPrefLoopAlignment(unsigned Align) {
1344 PrefLoopAlignment = Align;
1347 /// Set the minimum stack alignment of an argument (in log2(bytes)).
1348 void setMinStackArgumentAlignment(unsigned Align) {
1349 MinStackArgumentAlignment = Align;
1352 /// Set if the DAG builder should automatically insert fences and reduce the
1353 /// order of atomic memory operations to Monotonic.
1354 void setInsertFencesForAtomic(bool fence) {
1355 InsertFencesForAtomic = fence;
1359 //===--------------------------------------------------------------------===//
1360 // Addressing mode description hooks (used by LSR etc).
1363 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1364 /// instructions reading the address. This allows as much computation as
1365 /// possible to be done in the address mode for that operand. This hook lets
1366 /// targets also pass back when this should be done on intrinsics which
1368 virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/,
1369 SmallVectorImpl<Value*> &/*Ops*/,
1370 Type *&/*AccessTy*/) const {
1374 /// This represents an addressing mode of:
1375 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1376 /// If BaseGV is null, there is no BaseGV.
1377 /// If BaseOffs is zero, there is no base offset.
1378 /// If HasBaseReg is false, there is no base register.
1379 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1382 GlobalValue *BaseGV;
1386 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1389 /// Return true if the addressing mode represented by AM is legal for this
1390 /// target, for a load/store of the specified type.
1392 /// The type may be VoidTy, in which case only return true if the addressing
1393 /// mode is legal for a load/store of any legal type. TODO: Handle
1394 /// pre/postinc as well.
1395 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
1397 /// \brief Return the cost of the scaling factor used in the addressing mode
1398 /// represented by AM for this target, for a load/store of the specified type.
1400 /// If the AM is supported, the return value must be >= 0.
1401 /// If the AM is not supported, it returns a negative value.
1402 /// TODO: Handle pre/postinc as well.
1403 virtual int getScalingFactorCost(const AddrMode &AM, Type *Ty) const {
1404 // Default: assume that any scaling factor used in a legal AM is free.
1405 if (isLegalAddressingMode(AM, Ty)) return 0;
1409 /// Return true if the specified immediate is legal icmp immediate, that is
1410 /// the target has icmp instructions which can compare a register against the
1411 /// immediate without having to materialize the immediate into a register.
1412 virtual bool isLegalICmpImmediate(int64_t) const {
1416 /// Return true if the specified immediate is legal add immediate, that is the
1417 /// target has add instructions which can add a register with the immediate
1418 /// without having to materialize the immediate into a register.
1419 virtual bool isLegalAddImmediate(int64_t) const {
1423 /// Return true if it's significantly cheaper to shift a vector by a uniform
1424 /// scalar than by an amount which will vary across each lane. On x86, for
1425 /// example, there is a "psllw" instruction for the former case, but no simple
1426 /// instruction for a general "a << b" operation on vectors.
1427 virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
1431 /// Return true if it's free to truncate a value of type Ty1 to type
1432 /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1433 /// by referencing its sub-register AX.
1434 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1438 /// Return true if a truncation from Ty1 to Ty2 is permitted when deciding
1439 /// whether a call is in tail position. Typically this means that both results
1440 /// would be assigned to the same register or stack slot, but it could mean
1441 /// the target performs adequate checks of its own before proceeding with the
1443 virtual bool allowTruncateForTailCall(Type * /*Ty1*/, Type * /*Ty2*/) const {
1447 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
1451 /// Return true if any actual instruction that defines a value of type Ty1
1452 /// implicitly zero-extends the value to Ty2 in the result register.
1454 /// This does not necessarily include registers defined in unknown ways, such
1455 /// as incoming arguments, or copies from unknown virtual registers. Also, if
1456 /// isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to
1457 /// truncate instructions. e.g. on x86-64, all instructions that define 32-bit
1458 /// values implicit zero-extend the result out to 64 bits.
1459 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1463 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
1467 /// Return true if the target supplies and combines to a paired load
1468 /// two loaded values of type LoadedType next to each other in memory.
1469 /// RequiredAlignment gives the minimal alignment constraints that must be met
1470 /// to be able to select this paired load.
1472 /// This information is *not* used to generate actual paired loads, but it is
1473 /// used to generate a sequence of loads that is easier to combine into a
1475 /// For instance, something like this:
1476 /// a = load i64* addr
1477 /// b = trunc i64 a to i32
1478 /// c = lshr i64 a, 32
1479 /// d = trunc i64 c to i32
1480 /// will be optimized into:
1481 /// b = load i32* addr1
1482 /// d = load i32* addr2
1483 /// Where addr1 = addr2 +/- sizeof(i32).
1485 /// In other words, unless the target performs a post-isel load combining,
1486 /// this information should not be provided because it will generate more
1488 virtual bool hasPairedLoad(Type * /*LoadedType*/,
1489 unsigned & /*RequiredAligment*/) const {
1493 virtual bool hasPairedLoad(EVT /*LoadedType*/,
1494 unsigned & /*RequiredAligment*/) const {
1498 /// Return true if zero-extending the specific node Val to type VT2 is free
1499 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
1500 /// because it's folded such as X86 zero-extending loads).
1501 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1502 return isZExtFree(Val.getValueType(), VT2);
1505 /// Return true if an fpext operation is free (for instance, because
1506 /// single-precision floating-point numbers are implicitly extended to
1507 /// double-precision).
1508 virtual bool isFPExtFree(EVT VT) const {
1509 assert(VT.isFloatingPoint());
1513 /// Return true if an fneg operation is free to the point where it is never
1514 /// worthwhile to replace it with a bitwise operation.
1515 virtual bool isFNegFree(EVT VT) const {
1516 assert(VT.isFloatingPoint());
1520 /// Return true if an fabs operation is free to the point where it is never
1521 /// worthwhile to replace it with a bitwise operation.
1522 virtual bool isFAbsFree(EVT VT) const {
1523 assert(VT.isFloatingPoint());
1527 /// Return true if an FMA operation is faster than a pair of fmul and fadd
1528 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
1529 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
1531 /// NOTE: This may be called before legalization on types for which FMAs are
1532 /// not legal, but should return true if those types will eventually legalize
1533 /// to types that support FMAs. After legalization, it will only be called on
1534 /// types that support FMAs (via Legal or Custom actions)
1535 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
1539 /// Return true if it's profitable to narrow operations of type VT1 to
1540 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
1542 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1546 /// \brief Return true if it is beneficial to convert a load of a constant to
1547 /// just the constant itself.
1548 /// On some targets it might be more efficient to use a combination of
1549 /// arithmetic instructions to materialize the constant instead of loading it
1550 /// from a constant pool.
1551 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1556 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
1557 /// with this index. This is needed because EXTRACT_SUBVECTOR usually
1558 /// has custom lowering that depends on the index of the first element,
1559 /// and only the target knows which lowering is cheap.
1560 virtual bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const {
1564 //===--------------------------------------------------------------------===//
1565 // Runtime Library hooks
1568 /// Rename the default libcall routine name for the specified libcall.
1569 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1570 LibcallRoutineNames[Call] = Name;
1573 /// Get the libcall routine name for the specified libcall.
1574 const char *getLibcallName(RTLIB::Libcall Call) const {
1575 return LibcallRoutineNames[Call];
1578 /// Override the default CondCode to be used to test the result of the
1579 /// comparison libcall against zero.
1580 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1581 CmpLibcallCCs[Call] = CC;
1584 /// Get the CondCode that's to be used to test the result of the comparison
1585 /// libcall against zero.
1586 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1587 return CmpLibcallCCs[Call];
1590 /// Set the CallingConv that should be used for the specified libcall.
1591 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1592 LibcallCallingConvs[Call] = CC;
1595 /// Get the CallingConv that should be used for the specified libcall.
1596 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1597 return LibcallCallingConvs[Call];
1601 const TargetMachine &TM;
1602 const DataLayout *DL;
1604 /// True if this is a little endian target.
1605 bool IsLittleEndian;
1607 /// Tells the code generator not to expand operations into sequences that use
1608 /// the select operations if possible.
1609 bool SelectIsExpensive;
1611 /// Tells the code generator that the target has multiple (allocatable)
1612 /// condition registers that can be used to store the results of comparisons
1613 /// for use by selects and conditional branches. With multiple condition
1614 /// registers, the code generator will not aggressively sink comparisons into
1615 /// the blocks of their users.
1616 bool HasMultipleConditionRegisters;
1618 /// Tells the code generator that the target has BitExtract instructions.
1619 /// The code generator will aggressively sink "shift"s into the blocks of
1620 /// their users if the users will generate "and" instructions which can be
1621 /// combined with "shift" to BitExtract instructions.
1622 bool HasExtractBitsInsn;
1624 /// Tells the code generator not to expand integer divides by constants into a
1625 /// sequence of muls, adds, and shifts. This is a hack until a real cost
1626 /// model is in place. If we ever optimize for size, this will be set to true
1627 /// unconditionally.
1630 // Don't expand fsqrt with an approximation based on the inverse sqrt.
1633 /// Tells the code generator to bypass slow divide or remainder
1634 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
1635 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
1636 /// div/rem when the operands are positive and less than 256.
1637 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
1639 /// Tells the code generator that it shouldn't generate sra/srl/add/sra for a
1640 /// signed divide by power of two; let the target handle it.
1641 bool Pow2SDivIsCheap;
1643 /// Tells the code generator that it shouldn't generate extra flow control
1644 /// instructions and should attempt to combine flow control instructions via
1646 bool JumpIsExpensive;
1648 /// Whether the target supports or cares about preserving floating point
1649 /// exception behavior.
1650 bool HasFloatingPointExceptions;
1652 /// This target prefers to use _setjmp to implement llvm.setjmp.
1654 /// Defaults to false.
1655 bool UseUnderscoreSetJmp;
1657 /// This target prefers to use _longjmp to implement llvm.longjmp.
1659 /// Defaults to false.
1660 bool UseUnderscoreLongJmp;
1662 /// Number of blocks threshold to use jump tables.
1663 int MinimumJumpTableEntries;
1665 /// Information about the contents of the high-bits in boolean values held in
1666 /// a type wider than i1. See getBooleanContents.
1667 BooleanContent BooleanContents;
1669 /// Information about the contents of the high-bits in boolean values held in
1670 /// a type wider than i1. See getBooleanContents.
1671 BooleanContent BooleanFloatContents;
1673 /// Information about the contents of the high-bits in boolean vector values
1674 /// when the element type is wider than i1. See getBooleanContents.
1675 BooleanContent BooleanVectorContents;
1677 /// The target scheduling preference: shortest possible total cycles or lowest
1679 Sched::Preference SchedPreferenceInfo;
1681 /// The size, in bytes, of the target's jmp_buf buffers
1682 unsigned JumpBufSize;
1684 /// The alignment, in bytes, of the target's jmp_buf buffers
1685 unsigned JumpBufAlignment;
1687 /// The minimum alignment that any argument on the stack needs to have.
1688 unsigned MinStackArgumentAlignment;
1690 /// The minimum function alignment (used when optimizing for size, and to
1691 /// prevent explicitly provided alignment from leading to incorrect code).
1692 unsigned MinFunctionAlignment;
1694 /// The preferred function alignment (used when alignment unspecified and
1695 /// optimizing for speed).
1696 unsigned PrefFunctionAlignment;
1698 /// The preferred loop alignment.
1699 unsigned PrefLoopAlignment;
1701 /// Whether the DAG builder should automatically insert fences and reduce
1702 /// ordering for atomics. (This will be set for for most architectures with
1703 /// weak memory ordering.)
1704 bool InsertFencesForAtomic;
1706 /// If set to a physical register, this specifies the register that
1707 /// llvm.savestack/llvm.restorestack should save and restore.
1708 unsigned StackPointerRegisterToSaveRestore;
1710 /// If set to a physical register, this specifies the register that receives
1711 /// the exception address on entry to a landing pad.
1712 unsigned ExceptionPointerRegister;
1714 /// If set to a physical register, this specifies the register that receives
1715 /// the exception typeid on entry to a landing pad.
1716 unsigned ExceptionSelectorRegister;
1718 /// This indicates the default register class to use for each ValueType the
1719 /// target supports natively.
1720 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1721 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1722 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1724 /// This indicates the "representative" register class to use for each
1725 /// ValueType the target supports natively. This information is used by the
1726 /// scheduler to track register pressure. By default, the representative
1727 /// register class is the largest legal super-reg register class of the
1728 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
1729 /// representative class would be GR32.
1730 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1732 /// This indicates the "cost" of the "representative" register class for each
1733 /// ValueType. The cost is used by the scheduler to approximate register
1735 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1737 /// For any value types we are promoting or expanding, this contains the value
1738 /// type that we are changing to. For Expanded types, this contains one step
1739 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
1740 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
1741 /// the same type (e.g. i32 -> i32).
1742 MVT TransformToType[MVT::LAST_VALUETYPE];
1744 /// For each operation and each value type, keep a LegalizeAction that
1745 /// indicates how instruction selection should deal with the operation. Most
1746 /// operations are Legal (aka, supported natively by the target), but
1747 /// operations that are not should be described. Note that operations on
1748 /// non-legal value types are not described here.
1749 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1751 /// For each load extension type and each value type, keep a LegalizeAction
1752 /// that indicates how instruction selection should deal with a load of a
1753 /// specific value type and extension type.
1754 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]
1755 [ISD::LAST_LOADEXT_TYPE];
1757 /// For each value type pair keep a LegalizeAction that indicates whether a
1758 /// truncating store of a specific value type and truncating type is legal.
1759 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1761 /// For each indexed mode and each value type, keep a pair of LegalizeAction
1762 /// that indicates how instruction selection should deal with the load /
1765 /// The first dimension is the value_type for the reference. The second
1766 /// dimension represents the various modes for load store.
1767 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1769 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
1770 /// indicates how instruction selection should deal with the condition code.
1772 /// Because each CC action takes up 2 bits, we need to have the array size be
1773 /// large enough to fit all of the value types. This can be done by rounding
1774 /// up the MVT::LAST_VALUETYPE value to the next multiple of 16.
1775 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 15) / 16];
1777 ValueTypeActionImpl ValueTypeActions;
1781 getTypeConversion(LLVMContext &Context, EVT VT) const {
1782 // If this is a simple type, use the ComputeRegisterProp mechanism.
1783 if (VT.isSimple()) {
1784 MVT SVT = VT.getSimpleVT();
1785 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
1786 MVT NVT = TransformToType[SVT.SimpleTy];
1787 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
1790 (LA == TypeLegal || LA == TypeSoftenFloat ||
1791 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)
1792 && "Promote may not follow Expand or Promote");
1794 if (LA == TypeSplitVector)
1795 return LegalizeKind(LA, EVT::getVectorVT(Context,
1796 SVT.getVectorElementType(),
1797 SVT.getVectorNumElements()/2));
1798 if (LA == TypeScalarizeVector)
1799 return LegalizeKind(LA, SVT.getVectorElementType());
1800 return LegalizeKind(LA, NVT);
1803 // Handle Extended Scalar Types.
1804 if (!VT.isVector()) {
1805 assert(VT.isInteger() && "Float types must be simple");
1806 unsigned BitSize = VT.getSizeInBits();
1807 // First promote to a power-of-two size, then expand if necessary.
1808 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1809 EVT NVT = VT.getRoundIntegerType(Context);
1810 assert(NVT != VT && "Unable to round integer VT");
1811 LegalizeKind NextStep = getTypeConversion(Context, NVT);
1812 // Avoid multi-step promotion.
1813 if (NextStep.first == TypePromoteInteger) return NextStep;
1814 // Return rounded integer type.
1815 return LegalizeKind(TypePromoteInteger, NVT);
1818 return LegalizeKind(TypeExpandInteger,
1819 EVT::getIntegerVT(Context, VT.getSizeInBits()/2));
1822 // Handle vector types.
1823 unsigned NumElts = VT.getVectorNumElements();
1824 EVT EltVT = VT.getVectorElementType();
1826 // Vectors with only one element are always scalarized.
1828 return LegalizeKind(TypeScalarizeVector, EltVT);
1830 // Try to widen vector elements until the element type is a power of two and
1831 // promote it to a legal type later on, for example:
1832 // <3 x i8> -> <4 x i8> -> <4 x i32>
1833 if (EltVT.isInteger()) {
1834 // Vectors with a number of elements that is not a power of two are always
1835 // widened, for example <3 x i8> -> <4 x i8>.
1836 if (!VT.isPow2VectorType()) {
1837 NumElts = (unsigned)NextPowerOf2(NumElts);
1838 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1839 return LegalizeKind(TypeWidenVector, NVT);
1842 // Examine the element type.
1843 LegalizeKind LK = getTypeConversion(Context, EltVT);
1845 // If type is to be expanded, split the vector.
1846 // <4 x i140> -> <2 x i140>
1847 if (LK.first == TypeExpandInteger)
1848 return LegalizeKind(TypeSplitVector,
1849 EVT::getVectorVT(Context, EltVT, NumElts / 2));
1851 // Promote the integer element types until a legal vector type is found
1852 // or until the element integer type is too big. If a legal type was not
1853 // found, fallback to the usual mechanism of widening/splitting the
1855 EVT OldEltVT = EltVT;
1857 // Increase the bitwidth of the element to the next pow-of-two
1858 // (which is greater than 8 bits).
1859 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()
1860 ).getRoundIntegerType(Context);
1862 // Stop trying when getting a non-simple element type.
1863 // Note that vector elements may be greater than legal vector element
1864 // types. Example: X86 XMM registers hold 64bit element on 32bit
1866 if (!EltVT.isSimple()) break;
1868 // Build a new vector type and check if it is legal.
1869 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1870 // Found a legal promoted vector type.
1871 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1872 return LegalizeKind(TypePromoteInteger,
1873 EVT::getVectorVT(Context, EltVT, NumElts));
1876 // Reset the type to the unexpanded type if we did not find a legal vector
1877 // type with a promoted vector element type.
1881 // Try to widen the vector until a legal type is found.
1882 // If there is no wider legal type, split the vector.
1884 // Round up to the next power of 2.
1885 NumElts = (unsigned)NextPowerOf2(NumElts);
1887 // If there is no simple vector type with this many elements then there
1888 // cannot be a larger legal vector type. Note that this assumes that
1889 // there are no skipped intermediate vector types in the simple types.
1890 if (!EltVT.isSimple()) break;
1891 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1892 if (LargerVector == MVT()) break;
1894 // If this type is legal then widen the vector.
1895 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1896 return LegalizeKind(TypeWidenVector, LargerVector);
1899 // Widen odd vectors to next power of two.
1900 if (!VT.isPow2VectorType()) {
1901 EVT NVT = VT.getPow2VectorType(Context);
1902 return LegalizeKind(TypeWidenVector, NVT);
1905 // Vectors with illegal element types are expanded.
1906 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1907 return LegalizeKind(TypeSplitVector, NVT);
1911 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
1913 /// Targets can specify ISD nodes that they would like PerformDAGCombine
1914 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
1917 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1919 /// For operations that must be promoted to a specific type, this holds the
1920 /// destination type. This map should be sparse, so don't hold it as an
1923 /// Targets add entries to this map with AddPromotedToType(..), clients access
1924 /// this with getTypeToPromoteTo(..).
1925 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1928 /// Stores the name each libcall.
1929 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1931 /// The ISD::CondCode that should be used to test the result of each of the
1932 /// comparison libcall against zero.
1933 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1935 /// Stores the CallingConv that should be used for each libcall.
1936 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1939 /// \brief Specify maximum number of store instructions per memset call.
1941 /// When lowering \@llvm.memset this field specifies the maximum number of
1942 /// store operations that may be substituted for the call to memset. Targets
1943 /// must set this value based on the cost threshold for that target. Targets
1944 /// should assume that the memset will be done using as many of the largest
1945 /// store operations first, followed by smaller ones, if necessary, per
1946 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1947 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1948 /// store. This only applies to setting a constant array of a constant size.
1949 unsigned MaxStoresPerMemset;
1951 /// Maximum number of stores operations that may be substituted for the call
1952 /// to memset, used for functions with OptSize attribute.
1953 unsigned MaxStoresPerMemsetOptSize;
1955 /// \brief Specify maximum bytes of store instructions per memcpy call.
1957 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1958 /// store operations that may be substituted for a call to memcpy. Targets
1959 /// must set this value based on the cost threshold for that target. Targets
1960 /// should assume that the memcpy will be done using as many of the largest
1961 /// store operations first, followed by smaller ones, if necessary, per
1962 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1963 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1964 /// and one 1-byte store. This only applies to copying a constant array of
1966 unsigned MaxStoresPerMemcpy;
1968 /// Maximum number of store operations that may be substituted for a call to
1969 /// memcpy, used for functions with OptSize attribute.
1970 unsigned MaxStoresPerMemcpyOptSize;
1972 /// \brief Specify maximum bytes of store instructions per memmove call.
1974 /// When lowering \@llvm.memmove this field specifies the maximum number of
1975 /// store instructions that may be substituted for a call to memmove. Targets
1976 /// must set this value based on the cost threshold for that target. Targets
1977 /// should assume that the memmove will be done using as many of the largest
1978 /// store operations first, followed by smaller ones, if necessary, per
1979 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1980 /// with 8-bit alignment would result in nine 1-byte stores. This only
1981 /// applies to copying a constant array of constant size.
1982 unsigned MaxStoresPerMemmove;
1984 /// Maximum number of store instructions that may be substituted for a call to
1985 /// memmove, used for functions with OpSize attribute.
1986 unsigned MaxStoresPerMemmoveOptSize;
1988 /// Tells the code generator that select is more expensive than a branch if
1989 /// the branch is usually predicted right.
1990 bool PredictableSelectIsExpensive;
1992 /// MaskAndBranchFoldingIsLegal - Indicates if the target supports folding
1993 /// a mask of a single bit, a compare, and a branch into a single instruction.
1994 bool MaskAndBranchFoldingIsLegal;
1996 /// \see enableExtLdPromotion.
1997 bool EnableExtLdPromotion;
2000 /// Return true if the value types that can be represented by the specified
2001 /// register class are all legal.
2002 bool isLegalRC(const TargetRegisterClass *RC) const;
2004 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2005 /// sequence of memory operands that is recognized by PrologEpilogInserter.
2006 MachineBasicBlock *emitPatchPoint(MachineInstr *MI, MachineBasicBlock *MBB) const;
2009 /// This class defines information used to lower LLVM code to legal SelectionDAG
2010 /// operators that the target instruction selector can accept natively.
2012 /// This class also defines callbacks that targets must implement to lower
2013 /// target-specific constructs to SelectionDAG operators.
2014 class TargetLowering : public TargetLoweringBase {
2015 TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION;
2016 void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION;
2019 /// NOTE: The TargetMachine owns TLOF.
2020 explicit TargetLowering(const TargetMachine &TM);
2022 /// Returns true by value, base pointer and offset pointer and addressing mode
2023 /// by reference if the node's address can be legally represented as
2024 /// pre-indexed load / store address.
2025 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2026 SDValue &/*Offset*/,
2027 ISD::MemIndexedMode &/*AM*/,
2028 SelectionDAG &/*DAG*/) const {
2032 /// Returns true by value, base pointer and offset pointer and addressing mode
2033 /// by reference if this node can be combined with a load / store to form a
2034 /// post-indexed load / store.
2035 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2037 SDValue &/*Offset*/,
2038 ISD::MemIndexedMode &/*AM*/,
2039 SelectionDAG &/*DAG*/) const {
2043 /// Return the entry encoding for a jump table in the current function. The
2044 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2045 virtual unsigned getJumpTableEncoding() const;
2047 virtual const MCExpr *
2048 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
2049 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2050 MCContext &/*Ctx*/) const {
2051 llvm_unreachable("Need to implement this hook if target has custom JTIs");
2054 /// Returns relocation base for the given PIC jumptable.
2055 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2056 SelectionDAG &DAG) const;
2058 /// This returns the relocation base for the given PIC jumptable, the same as
2059 /// getPICJumpTableRelocBase, but as an MCExpr.
2060 virtual const MCExpr *
2061 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2062 unsigned JTI, MCContext &Ctx) const;
2064 /// Return true if folding a constant offset with the given GlobalAddress is
2065 /// legal. It is frequently not legal in PIC relocation models.
2066 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2068 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2069 SDValue &Chain) const;
2071 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
2072 SDValue &NewLHS, SDValue &NewRHS,
2073 ISD::CondCode &CCCode, SDLoc DL) const;
2075 /// Returns a pair of (return value, chain).
2076 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2077 EVT RetVT, const SDValue *Ops,
2078 unsigned NumOps, bool isSigned,
2079 SDLoc dl, bool doesNotReturn = false,
2080 bool isReturnValueUsed = true) const;
2082 //===--------------------------------------------------------------------===//
2083 // TargetLowering Optimization Methods
2086 /// A convenience struct that encapsulates a DAG, and two SDValues for
2087 /// returning information from TargetLowering to its clients that want to
2089 struct TargetLoweringOpt {
2096 explicit TargetLoweringOpt(SelectionDAG &InDAG,
2098 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2100 bool LegalTypes() const { return LegalTys; }
2101 bool LegalOperations() const { return LegalOps; }
2103 bool CombineTo(SDValue O, SDValue N) {
2109 /// Check to see if the specified operand of the specified instruction is a
2110 /// constant integer. If so, check to see if there are any bits set in the
2111 /// constant that are not demanded. If so, shrink the constant and return
2113 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
2115 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2116 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2117 /// generalized for targets with other types of implicit widening casts.
2118 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2122 /// Look at Op. At this point, we know that only the DemandedMask bits of the
2123 /// result of Op are ever used downstream. If we can use this information to
2124 /// simplify Op, create a new simplified DAG node and return true, returning
2125 /// the original and new nodes in Old and New. Otherwise, analyze the
2126 /// expression and return a mask of KnownOne and KnownZero bits for the
2127 /// expression (used to simplify the caller). The KnownZero/One bits may only
2128 /// be accurate for those bits in the DemandedMask.
2129 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2130 APInt &KnownZero, APInt &KnownOne,
2131 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2133 /// Determine which of the bits specified in Mask are known to be either zero
2134 /// or one and return them in the KnownZero/KnownOne bitsets.
2135 virtual void computeKnownBitsForTargetNode(const SDValue Op,
2138 const SelectionDAG &DAG,
2139 unsigned Depth = 0) const;
2141 /// This method can be implemented by targets that want to expose additional
2142 /// information about sign bits to the DAG Combiner.
2143 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2144 const SelectionDAG &DAG,
2145 unsigned Depth = 0) const;
2147 struct DAGCombinerInfo {
2148 void *DC; // The DAG Combiner object.
2150 bool CalledByLegalizer;
2154 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
2155 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2157 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2158 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2159 bool isAfterLegalizeVectorOps() const {
2160 return Level == AfterLegalizeDAG;
2162 CombineLevel getDAGCombineLevel() { return Level; }
2163 bool isCalledByLegalizer() const { return CalledByLegalizer; }
2165 void AddToWorklist(SDNode *N);
2166 void RemoveFromWorklist(SDNode *N);
2167 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
2169 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2170 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2172 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2175 /// Return if the N is a constant or constant vector equal to the true value
2176 /// from getBooleanContents().
2177 bool isConstTrueVal(const SDNode *N) const;
2179 /// Return if the N is a constant or constant vector equal to the false value
2180 /// from getBooleanContents().
2181 bool isConstFalseVal(const SDNode *N) const;
2183 /// Try to simplify a setcc built with the specified operands and cc. If it is
2184 /// unable to simplify it, return a null SDValue.
2185 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
2186 ISD::CondCode Cond, bool foldBooleans,
2187 DAGCombinerInfo &DCI, SDLoc dl) const;
2189 /// Returns true (and the GlobalValue and the offset) if the node is a
2190 /// GlobalAddress + offset.
2192 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2194 /// This method will be invoked for all target nodes and for any
2195 /// target-independent nodes that the target has registered with invoke it
2198 /// The semantics are as follows:
2200 /// SDValue.Val == 0 - No change was made
2201 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2202 /// otherwise - N should be replaced by the returned Operand.
2204 /// In addition, methods provided by DAGCombinerInfo may be used to perform
2205 /// more complex transformations.
2207 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2209 /// Return true if it is profitable to move a following shift through this
2210 // node, adjusting any immediate operands as necessary to preserve semantics.
2211 // This transformation may not be desirable if it disrupts a particularly
2212 // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
2213 // By default, it returns true.
2214 virtual bool isDesirableToCommuteWithShift(const SDNode *N /*Op*/) const {
2218 /// Return true if the target has native support for the specified value type
2219 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2220 /// i16 is legal, but undesirable since i16 instruction encodings are longer
2221 /// and some i16 instructions are slow.
2222 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2223 // By default, assume all legal types are desirable.
2224 return isTypeLegal(VT);
2227 /// Return true if it is profitable for dag combiner to transform a floating
2228 /// point op of specified opcode to a equivalent op of an integer
2229 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2230 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2235 /// This method query the target whether it is beneficial for dag combiner to
2236 /// promote the specified node. If true, it should return the desired
2237 /// promotion type by reference.
2238 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
2242 //===--------------------------------------------------------------------===//
2243 // Lowering methods - These methods must be implemented by targets so that
2244 // the SelectionDAGBuilder code knows how to lower these.
2247 /// This hook must be implemented to lower the incoming (formal) arguments,
2248 /// described by the Ins array, into the specified DAG. The implementation
2249 /// should fill in the InVals array with legal-type argument values, and
2250 /// return the resulting token chain value.
2253 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2255 const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
2256 SDLoc /*dl*/, SelectionDAG &/*DAG*/,
2257 SmallVectorImpl<SDValue> &/*InVals*/) const {
2258 llvm_unreachable("Not Implemented");
2261 struct ArgListEntry {
2270 bool isInAlloca : 1;
2271 bool isReturned : 1;
2274 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
2275 isSRet(false), isNest(false), isByVal(false), isInAlloca(false),
2276 isReturned(false), Alignment(0) { }
2278 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
2280 typedef std::vector<ArgListEntry> ArgListTy;
2282 /// This structure contains all information that is necessary for lowering
2283 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
2284 /// needs to lower a call, and targets will see this struct in their LowerCall
2286 struct CallLoweringInfo {
2293 bool DoesNotReturn : 1;
2294 bool IsReturnValueUsed : 1;
2296 // IsTailCall should be modified by implementations of
2297 // TargetLowering::LowerCall that perform tail call conversions.
2300 unsigned NumFixedArgs;
2301 CallingConv::ID CallConv;
2306 ImmutableCallSite *CS;
2308 SmallVector<ISD::OutputArg, 32> Outs;
2309 SmallVector<SDValue, 32> OutVals;
2310 SmallVector<ISD::InputArg, 32> Ins;
2312 CallLoweringInfo(SelectionDAG &DAG)
2313 : RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false),
2314 IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true),
2315 IsTailCall(false), NumFixedArgs(-1), CallConv(CallingConv::C),
2316 DAG(DAG), CS(nullptr), IsPatchPoint(false) {}
2318 CallLoweringInfo &setDebugLoc(SDLoc dl) {
2323 CallLoweringInfo &setChain(SDValue InChain) {
2328 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
2329 SDValue Target, ArgListTy &&ArgsList,
2330 unsigned FixedArgs = -1) {
2335 (FixedArgs == static_cast<unsigned>(-1) ? Args.size() : FixedArgs);
2336 Args = std::move(ArgsList);
2340 CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
2341 SDValue Target, ArgListTy &&ArgsList,
2342 ImmutableCallSite &Call) {
2345 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
2346 DoesNotReturn = Call.doesNotReturn();
2347 IsVarArg = FTy->isVarArg();
2348 IsReturnValueUsed = !Call.getInstruction()->use_empty();
2349 RetSExt = Call.paramHasAttr(0, Attribute::SExt);
2350 RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
2354 CallConv = Call.getCallingConv();
2355 NumFixedArgs = FTy->getNumParams();
2356 Args = std::move(ArgsList);
2363 CallLoweringInfo &setInRegister(bool Value = true) {
2368 CallLoweringInfo &setNoReturn(bool Value = true) {
2369 DoesNotReturn = Value;
2373 CallLoweringInfo &setVarArg(bool Value = true) {
2378 CallLoweringInfo &setTailCall(bool Value = true) {
2383 CallLoweringInfo &setDiscardResult(bool Value = true) {
2384 IsReturnValueUsed = !Value;
2388 CallLoweringInfo &setSExtResult(bool Value = true) {
2393 CallLoweringInfo &setZExtResult(bool Value = true) {
2398 CallLoweringInfo &setIsPatchPoint(bool Value = true) {
2399 IsPatchPoint = Value;
2403 ArgListTy &getArgs() {
2408 /// This function lowers an abstract call to a function into an actual call.
2409 /// This returns a pair of operands. The first element is the return value
2410 /// for the function (if RetTy is not VoidTy). The second element is the
2411 /// outgoing token chain. It calls LowerCall to do the actual lowering.
2412 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
2414 /// This hook must be implemented to lower calls into the the specified
2415 /// DAG. The outgoing arguments to the call are described by the Outs array,
2416 /// and the values to be returned by the call are described by the Ins
2417 /// array. The implementation should fill in the InVals array with legal-type
2418 /// return values from the call, and return the resulting token chain value.
2420 LowerCall(CallLoweringInfo &/*CLI*/,
2421 SmallVectorImpl<SDValue> &/*InVals*/) const {
2422 llvm_unreachable("Not Implemented");
2425 /// Target-specific cleanup for formal ByVal parameters.
2426 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
2428 /// This hook should be implemented to check whether the return values
2429 /// described by the Outs array can fit into the return registers. If false
2430 /// is returned, an sret-demotion is performed.
2431 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
2432 MachineFunction &/*MF*/, bool /*isVarArg*/,
2433 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2434 LLVMContext &/*Context*/) const
2436 // Return true by default to get preexisting behavior.
2440 /// This hook must be implemented to lower outgoing return values, described
2441 /// by the Outs array, into the specified DAG. The implementation should
2442 /// return the resulting token chain value.
2444 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2446 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2447 const SmallVectorImpl<SDValue> &/*OutVals*/,
2448 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const {
2449 llvm_unreachable("Not Implemented");
2452 /// Return true if result of the specified node is used by a return node
2453 /// only. It also compute and return the input chain for the tail call.
2455 /// This is used to determine whether it is possible to codegen a libcall as
2456 /// tail call at legalization time.
2457 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
2461 /// Return true if the target may be able emit the call instruction as a tail
2462 /// call. This is used by optimization passes to determine if it's profitable
2463 /// to duplicate return instructions to enable tailcall optimization.
2464 virtual bool mayBeEmittedAsTailCall(CallInst *) const {
2468 /// Return the builtin name for the __builtin___clear_cache intrinsic
2469 /// Default is to invoke the clear cache library call
2470 virtual const char * getClearCacheBuiltinName() const {
2471 return "__clear_cache";
2474 /// Return the register ID of the name passed in. Used by named register
2475 /// global variables extension. There is no target-independent behaviour
2476 /// so the default action is to bail.
2477 virtual unsigned getRegisterByName(const char* RegName, EVT VT) const {
2478 report_fatal_error("Named registers not implemented for this target");
2481 /// Return the type that should be used to zero or sign extend a
2482 /// zeroext/signext integer argument or return value. FIXME: Most C calling
2483 /// convention requires the return type to be promoted, but this is not true
2484 /// all the time, e.g. i1 on x86-64. It is also not necessary for non-C
2485 /// calling conventions. The frontend should handle this and include all of
2486 /// the necessary information.
2487 virtual EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2488 ISD::NodeType /*ExtendKind*/) const {
2489 EVT MinVT = getRegisterType(Context, MVT::i32);
2490 return VT.bitsLT(MinVT) ? MinVT : VT;
2493 /// For some targets, an LLVM struct type must be broken down into multiple
2494 /// simple types, but the calling convention specifies that the entire struct
2495 /// must be passed in a block of consecutive registers.
2497 functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
2498 bool isVarArg) const {
2502 /// Returns a 0 terminated array of registers that can be safely used as
2503 /// scratch registers.
2504 virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
2508 /// This callback is used to prepare for a volatile or atomic load.
2509 /// It takes a chain node as input and returns the chain for the load itself.
2511 /// Having a callback like this is necessary for targets like SystemZ,
2512 /// which allows a CPU to reuse the result of a previous load indefinitely,
2513 /// even if a cache-coherent store is performed by another CPU. The default
2514 /// implementation does nothing.
2515 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
2516 SelectionDAG &DAG) const {
2520 /// This callback is invoked by the type legalizer to legalize nodes with an
2521 /// illegal operand type but legal result types. It replaces the
2522 /// LowerOperation callback in the type Legalizer. The reason we can not do
2523 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
2524 /// use this callback.
2526 /// TODO: Consider merging with ReplaceNodeResults.
2528 /// The target places new result values for the node in Results (their number
2529 /// and types must exactly match those of the original return values of
2530 /// the node), or leaves Results empty, which indicates that the node is not
2531 /// to be custom lowered after all.
2532 /// The default implementation calls LowerOperation.
2533 virtual void LowerOperationWrapper(SDNode *N,
2534 SmallVectorImpl<SDValue> &Results,
2535 SelectionDAG &DAG) const;
2537 /// This callback is invoked for operations that are unsupported by the
2538 /// target, which are registered to use 'custom' lowering, and whose defined
2539 /// values are all legal. If the target has no operations that require custom
2540 /// lowering, it need not implement this. The default implementation of this
2542 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
2544 /// This callback is invoked when a node result type is illegal for the
2545 /// target, and the operation was registered to use 'custom' lowering for that
2546 /// result type. The target places new result values for the node in Results
2547 /// (their number and types must exactly match those of the original return
2548 /// values of the node), or leaves Results empty, which indicates that the
2549 /// node is not to be custom lowered after all.
2551 /// If the target has no operations that require custom lowering, it need not
2552 /// implement this. The default implementation aborts.
2553 virtual void ReplaceNodeResults(SDNode * /*N*/,
2554 SmallVectorImpl<SDValue> &/*Results*/,
2555 SelectionDAG &/*DAG*/) const {
2556 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
2559 /// This method returns the name of a target specific DAG node.
2560 virtual const char *getTargetNodeName(unsigned Opcode) const;
2562 /// This method returns a target specific FastISel object, or null if the
2563 /// target does not support "fast" ISel.
2564 virtual FastISel *createFastISel(FunctionLoweringInfo &,
2565 const TargetLibraryInfo *) const {
2570 bool verifyReturnAddressArgumentIsConstant(SDValue Op,
2571 SelectionDAG &DAG) const;
2573 //===--------------------------------------------------------------------===//
2574 // Inline Asm Support hooks
2577 /// This hook allows the target to expand an inline asm call to be explicit
2578 /// llvm code if it wants to. This is useful for turning simple inline asms
2579 /// into LLVM intrinsics, which gives the compiler more information about the
2580 /// behavior of the code.
2581 virtual bool ExpandInlineAsm(CallInst *) const {
2585 enum ConstraintType {
2586 C_Register, // Constraint represents specific register(s).
2587 C_RegisterClass, // Constraint represents any of register(s) in class.
2588 C_Memory, // Memory constraint.
2589 C_Other, // Something else.
2590 C_Unknown // Unsupported constraint.
2593 enum ConstraintWeight {
2595 CW_Invalid = -1, // No match.
2596 CW_Okay = 0, // Acceptable.
2597 CW_Good = 1, // Good weight.
2598 CW_Better = 2, // Better weight.
2599 CW_Best = 3, // Best weight.
2601 // Well-known weights.
2602 CW_SpecificReg = CW_Okay, // Specific register operands.
2603 CW_Register = CW_Good, // Register operands.
2604 CW_Memory = CW_Better, // Memory operands.
2605 CW_Constant = CW_Best, // Constant operand.
2606 CW_Default = CW_Okay // Default or don't know type.
2609 /// This contains information for each constraint that we are lowering.
2610 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
2611 /// This contains the actual string for the code, like "m". TargetLowering
2612 /// picks the 'best' code from ConstraintInfo::Codes that most closely
2613 /// matches the operand.
2614 std::string ConstraintCode;
2616 /// Information about the constraint code, e.g. Register, RegisterClass,
2617 /// Memory, Other, Unknown.
2618 TargetLowering::ConstraintType ConstraintType;
2620 /// If this is the result output operand or a clobber, this is null,
2621 /// otherwise it is the incoming operand to the CallInst. This gets
2622 /// modified as the asm is processed.
2623 Value *CallOperandVal;
2625 /// The ValueType for the operand value.
2628 /// Return true of this is an input operand that is a matching constraint
2630 bool isMatchingInputConstraint() const;
2632 /// If this is an input matching constraint, this method returns the output
2633 /// operand it matches.
2634 unsigned getMatchedOperand() const;
2636 /// Copy constructor for copying from a ConstraintInfo.
2637 AsmOperandInfo(InlineAsm::ConstraintInfo Info)
2638 : InlineAsm::ConstraintInfo(std::move(Info)),
2639 ConstraintType(TargetLowering::C_Unknown), CallOperandVal(nullptr),
2640 ConstraintVT(MVT::Other) {}
2643 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
2645 /// Split up the constraint string from the inline assembly value into the
2646 /// specific constraints and their prefixes, and also tie in the associated
2647 /// operand values. If this returns an empty vector, and if the constraint
2648 /// string itself isn't empty, there was an error parsing.
2649 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const;
2651 /// Examine constraint type and operand type and determine a weight value.
2652 /// The operand object must already have been set up with the operand type.
2653 virtual ConstraintWeight getMultipleConstraintMatchWeight(
2654 AsmOperandInfo &info, int maIndex) const;
2656 /// Examine constraint string and operand type and determine a weight value.
2657 /// The operand object must already have been set up with the operand type.
2658 virtual ConstraintWeight getSingleConstraintMatchWeight(
2659 AsmOperandInfo &info, const char *constraint) const;
2661 /// Determines the constraint code and constraint type to use for the specific
2662 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
2663 /// If the actual operand being passed in is available, it can be passed in as
2664 /// Op, otherwise an empty SDValue can be passed.
2665 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2667 SelectionDAG *DAG = nullptr) const;
2669 /// Given a constraint, return the type of constraint it is for this target.
2670 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
2672 /// Given a physical register constraint (e.g. {edx}), return the register
2673 /// number and the register class for the register.
2675 /// Given a register class constraint, like 'r', if this corresponds directly
2676 /// to an LLVM register class, return a register of 0 and the register class
2679 /// This should only be used for C_Register constraints. On error, this
2680 /// returns a register number of 0 and a null register class pointer.
2681 virtual std::pair<unsigned, const TargetRegisterClass*>
2682 getRegForInlineAsmConstraint(const std::string &Constraint,
2685 /// Try to replace an X constraint, which matches anything, with another that
2686 /// has more specific requirements based on the type of the corresponding
2687 /// operand. This returns null if there is no replacement to make.
2688 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
2690 /// Lower the specified operand into the Ops vector. If it is invalid, don't
2691 /// add anything to Ops.
2692 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
2693 std::vector<SDValue> &Ops,
2694 SelectionDAG &DAG) const;
2696 //===--------------------------------------------------------------------===//
2697 // Div utility functions
2699 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2700 SelectionDAG &DAG) const;
2701 SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2702 bool IsAfterLegalization,
2703 std::vector<SDNode *> *Created) const;
2704 SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2705 bool IsAfterLegalization,
2706 std::vector<SDNode *> *Created) const;
2707 virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
2709 std::vector<SDNode *> *Created) const {
2713 /// Indicate whether this target prefers to combine the given number of FDIVs
2714 /// with the same divisor.
2715 virtual bool combineRepeatedFPDivisors(unsigned NumUsers) const {
2719 /// Hooks for building estimates in place of slower divisions and square
2722 /// Return a reciprocal square root estimate value for the input operand.
2723 /// The RefinementSteps output is the number of Newton-Raphson refinement
2724 /// iterations required to generate a sufficient (though not necessarily
2725 /// IEEE-754 compliant) estimate for the value type.
2726 /// The boolean UseOneConstNR output is used to select a Newton-Raphson
2727 /// algorithm implementation that uses one constant or two constants.
2728 /// A target may choose to implement its own refinement within this function.
2729 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2730 /// any further refinement of the estimate.
2731 /// An empty SDValue return means no estimate sequence can be created.
2732 virtual SDValue getRsqrtEstimate(SDValue Operand,
2733 DAGCombinerInfo &DCI,
2734 unsigned &RefinementSteps,
2735 bool &UseOneConstNR) const {
2739 /// Return a reciprocal estimate value for the input operand.
2740 /// The RefinementSteps output is the number of Newton-Raphson refinement
2741 /// iterations required to generate a sufficient (though not necessarily
2742 /// IEEE-754 compliant) estimate for the value type.
2743 /// A target may choose to implement its own refinement within this function.
2744 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2745 /// any further refinement of the estimate.
2746 /// An empty SDValue return means no estimate sequence can be created.
2747 virtual SDValue getRecipEstimate(SDValue Operand,
2748 DAGCombinerInfo &DCI,
2749 unsigned &RefinementSteps) const {
2753 //===--------------------------------------------------------------------===//
2754 // Legalization utility functions
2757 /// Expand a MUL into two nodes. One that computes the high bits of
2758 /// the result and one that computes the low bits.
2759 /// \param HiLoVT The value type to use for the Lo and Hi nodes.
2760 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
2761 /// if you want to control how low bits are extracted from the LHS.
2762 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
2763 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
2764 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
2765 /// \returns true if the node has been expanded. false if it has not
2766 bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2767 SelectionDAG &DAG, SDValue LL = SDValue(),
2768 SDValue LH = SDValue(), SDValue RL = SDValue(),
2769 SDValue RH = SDValue()) const;
2771 /// Expand float(f32) to SINT(i64) conversion
2772 /// \param N Node to expand
2773 /// \param Result output after conversion
2774 /// \returns True, if the expansion was successful, false otherwise
2775 bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
2777 //===--------------------------------------------------------------------===//
2778 // Instruction Emitting Hooks
2781 /// This method should be implemented by targets that mark instructions with
2782 /// the 'usesCustomInserter' flag. These instructions are special in various
2783 /// ways, which require special support to insert. The specified MachineInstr
2784 /// is created but not inserted into any basic blocks, and this method is
2785 /// called to expand it into a sequence of instructions, potentially also
2786 /// creating new basic blocks and control flow.
2787 virtual MachineBasicBlock *
2788 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
2790 /// This method should be implemented by targets that mark instructions with
2791 /// the 'hasPostISelHook' flag. These instructions must be adjusted after
2792 /// instruction selection by target hooks. e.g. To fill in optional defs for
2793 /// ARM 's' setting instructions.
2795 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
2797 /// If this function returns true, SelectionDAGBuilder emits a
2798 /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
2799 virtual bool useLoadStackGuardNode() const {
2804 /// Given an LLVM IR type and return type attributes, compute the return value
2805 /// EVTs and flags, and optionally also the offsets, if the return value is
2806 /// being lowered to memory.
2807 void GetReturnInfo(Type* ReturnType, AttributeSet attr,
2808 SmallVectorImpl<ISD::OutputArg> &Outs,
2809 const TargetLowering &TLI);
2811 } // end llvm namespace