1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instructions to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Support/DataTypes.h"
27 class TargetRegisterClass;
29 class CalleeSavedInfo;
31 template<class T> class SmallVectorImpl;
33 //---------------------------------------------------------------------------
34 // Data types used to define information about a single machine instruction
35 //---------------------------------------------------------------------------
37 typedef short MachineOpCode;
38 typedef unsigned InstrSchedClass;
40 //---------------------------------------------------------------------------
41 // struct TargetInstrDescriptor:
42 // Predefined information about each machine instruction.
43 // Designed to initialized statically.
46 const unsigned M_BRANCH_FLAG = 1 << 0;
47 const unsigned M_CALL_FLAG = 1 << 1;
48 const unsigned M_RET_FLAG = 1 << 2;
49 const unsigned M_BARRIER_FLAG = 1 << 3;
50 const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
51 const unsigned M_LOAD_FLAG = 1 << 5;
52 const unsigned M_STORE_FLAG = 1 << 6;
53 const unsigned M_INDIRECT_FLAG = 1 << 7;
54 const unsigned M_IMPLICIT_DEF_FLAG = 1 << 8;
56 // M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be
57 // changed into a 3-address instruction if the first two operands cannot be
58 // assigned to the same register. The target must implement the
59 // TargetInstrInfo::convertToThreeAddress method for this instruction.
60 const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 9;
62 // This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
63 // Z), which produces the same result if Y and Z are exchanged.
64 const unsigned M_COMMUTABLE = 1 << 10;
66 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
67 // block? Typically this is things like return and branch instructions.
68 // Various passes use this to insert code into the bottom of a basic block, but
69 // before control flow occurs.
70 const unsigned M_TERMINATOR_FLAG = 1 << 11;
72 // M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
73 // insertion support when the DAG scheduler is inserting it into a machine basic
75 const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 12;
77 // M_VARIABLE_OPS - Set if this instruction can have a variable number of extra
78 // operands in addition to the minimum number operands specified.
79 const unsigned M_VARIABLE_OPS = 1 << 13;
81 // M_PREDICABLE - Set if this instruction has a predicate operand that
82 // controls execution. It may be set to 'always'.
83 const unsigned M_PREDICABLE = 1 << 14;
85 // M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized
86 // at any time, e.g. constant generation, load from constant pool.
87 const unsigned M_REMATERIALIZIBLE = 1 << 15;
89 // M_NOT_DUPLICABLE - Set if this instruction cannot be safely duplicated.
90 // (e.g. instructions with unique labels attached).
91 const unsigned M_NOT_DUPLICABLE = 1 << 16;
93 // M_HAS_OPTIONAL_DEF - Set if this instruction has an optional definition, e.g.
94 // ARM instructions which can set condition code if 's' bit is set.
95 const unsigned M_HAS_OPTIONAL_DEF = 1 << 17;
97 // M_NEVER_HAS_SIDE_EFFECTS - Set if this instruction has no side effects that
98 // are not captured by any operands of the instruction or other flags, and when
99 // *all* instances of the instruction of that opcode have no side effects.
101 // Note: This and M_MAY_HAVE_SIDE_EFFECTS are mutually exclusive. You can't set
102 // both! If neither flag is set, then the instruction *always* has side effects.
103 const unsigned M_NEVER_HAS_SIDE_EFFECTS = 1 << 18;
105 // M_MAY_HAVE_SIDE_EFFECTS - Set if some instances of this instruction can have
106 // side effects. The virtual method "isReallySideEffectFree" is called to
107 // determine this. Load instructions are an example of where this is useful. In
108 // general, loads always have side effects. However, loads from constant pools
109 // don't. We let the specific back end make this determination.
111 // Note: This and M_NEVER_HAS_SIDE_EFFECTS are mutually exclusive. You can't set
112 // both! If neither flag is set, then the instruction *always* has side effects.
113 const unsigned M_MAY_HAVE_SIDE_EFFECTS = 1 << 19;
115 // Machine operand flags
116 // M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it
117 // requires a callback to look up its register class.
118 const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0;
120 /// M_PREDICATE_OPERAND - Set if this is one of the operands that made up of the
121 /// predicate operand that controls an M_PREDICATED instruction.
122 const unsigned M_PREDICATE_OPERAND = 1 << 1;
124 /// M_OPTIONAL_DEF_OPERAND - Set if this operand is a optional def.
126 const unsigned M_OPTIONAL_DEF_OPERAND = 1 << 2;
129 // Operand constraints: only "tied_to" for now.
130 enum OperandConstraint {
131 TIED_TO = 0 // Must be allocated the same register as.
135 /// TargetOperandInfo - This holds information about one operand of a machine
136 /// instruction, indicating the register class for register operands, etc.
138 class TargetOperandInfo {
140 /// RegClass - This specifies the register class enumeration of the operand
141 /// if the operand is a register. If not, this contains 0.
142 unsigned short RegClass;
143 unsigned short Flags;
144 /// Lower 16 bits are used to specify which constraints are set. The higher 16
145 /// bits are used to specify the value of constraints (4 bits each).
146 unsigned int Constraints;
147 /// Currently no other information.
151 class TargetInstrDescriptor {
153 MachineOpCode Opcode; // The opcode.
154 unsigned short numOperands; // Num of args (may be more if variable_ops).
155 unsigned short numDefs; // Num of args that are definitions.
156 const char * Name; // Assembly language mnemonic for the opcode.
157 InstrSchedClass schedClass; // enum identifying instr sched class
158 unsigned Flags; // flags identifying machine instr class
159 unsigned TSFlags; // Target Specific Flag values
160 const unsigned *ImplicitUses; // Registers implicitly read by this instr
161 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
162 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
164 /// getOperandConstraint - Returns the value of the specific constraint if
165 /// it is set. Returns -1 if it is not set.
166 int getOperandConstraint(unsigned OpNum,
167 TOI::OperandConstraint Constraint) const {
168 assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) &&
169 "Invalid operand # of TargetInstrInfo");
170 if (OpNum < numOperands &&
171 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
172 unsigned Pos = 16 + Constraint * 4;
173 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
178 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
179 /// dest operand. Returns -1 if there isn't one.
180 int findTiedToSrcOperand(unsigned OpNum) const;
184 //---------------------------------------------------------------------------
186 /// TargetInstrInfo - Interface to description of machine instructions
188 class TargetInstrInfo {
189 const TargetInstrDescriptor* desc; // raw array to allow static init'n
190 unsigned NumOpcodes; // number of entries in the desc array
191 unsigned numRealOpCodes; // number of non-dummy op codes
193 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
194 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
196 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
197 virtual ~TargetInstrInfo();
199 // Invariant opcodes: All instruction sets have these as their low opcodes.
208 unsigned getNumOpcodes() const { return NumOpcodes; }
210 /// get - Return the machine instruction descriptor that corresponds to the
211 /// specified instruction opcode.
213 const TargetInstrDescriptor& get(MachineOpCode Opcode) const {
214 assert((unsigned)Opcode < NumOpcodes);
218 const char *getName(MachineOpCode Opcode) const {
219 return get(Opcode).Name;
222 int getNumOperands(MachineOpCode Opcode) const {
223 return get(Opcode).numOperands;
226 int getNumDefs(MachineOpCode Opcode) const {
227 return get(Opcode).numDefs;
230 InstrSchedClass getSchedClass(MachineOpCode Opcode) const {
231 return get(Opcode).schedClass;
234 const unsigned *getImplicitUses(MachineOpCode Opcode) const {
235 return get(Opcode).ImplicitUses;
238 const unsigned *getImplicitDefs(MachineOpCode Opcode) const {
239 return get(Opcode).ImplicitDefs;
244 // Query instruction class flags according to the machine-independent
245 // flags listed above.
247 bool isReturn(MachineOpCode Opcode) const {
248 return get(Opcode).Flags & M_RET_FLAG;
251 bool isCommutableInstr(MachineOpCode Opcode) const {
252 return get(Opcode).Flags & M_COMMUTABLE;
254 bool isTerminatorInstr(MachineOpCode Opcode) const {
255 return get(Opcode).Flags & M_TERMINATOR_FLAG;
258 bool isBranch(MachineOpCode Opcode) const {
259 return get(Opcode).Flags & M_BRANCH_FLAG;
262 bool isIndirectBranch(MachineOpCode Opcode) const {
263 return get(Opcode).Flags & M_INDIRECT_FLAG;
266 /// isBarrier - Returns true if the specified instruction stops control flow
267 /// from executing the instruction immediately following it. Examples include
268 /// unconditional branches and return instructions.
269 bool isBarrier(MachineOpCode Opcode) const {
270 return get(Opcode).Flags & M_BARRIER_FLAG;
273 bool isCall(MachineOpCode Opcode) const {
274 return get(Opcode).Flags & M_CALL_FLAG;
276 bool isLoad(MachineOpCode Opcode) const {
277 return get(Opcode).Flags & M_LOAD_FLAG;
279 bool isStore(MachineOpCode Opcode) const {
280 return get(Opcode).Flags & M_STORE_FLAG;
283 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
284 /// which must be filled by the code generator.
285 bool hasDelaySlot(MachineOpCode Opcode) const {
286 return get(Opcode).Flags & M_DELAY_SLOT_FLAG;
289 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
290 /// custom insertion support when the DAG scheduler is inserting it into a
291 /// machine basic block.
292 bool usesCustomDAGSchedInsertionHook(MachineOpCode Opcode) const {
293 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
296 bool hasVariableOperands(MachineOpCode Opcode) const {
297 return get(Opcode).Flags & M_VARIABLE_OPS;
300 bool isPredicable(MachineOpCode Opcode) const {
301 return get(Opcode).Flags & M_PREDICABLE;
304 bool isNotDuplicable(MachineOpCode Opcode) const {
305 return get(Opcode).Flags & M_NOT_DUPLICABLE;
308 bool hasOptionalDef(MachineOpCode Opcode) const {
309 return get(Opcode).Flags & M_HAS_OPTIONAL_DEF;
312 /// isTriviallyReMaterializable - Return true if the instruction is trivially
313 /// rematerializable, meaning it has no side effects and requires no operands
314 /// that aren't always available.
315 bool isTriviallyReMaterializable(MachineInstr *MI) const {
316 return (MI->getInstrDescriptor()->Flags & M_REMATERIALIZIBLE) &&
317 isReallyTriviallyReMaterializable(MI);
320 /// hasUnmodelledSideEffects - Returns true if the instruction has side
321 /// effects that are not captured by any operands of the instruction or other
323 bool hasUnmodelledSideEffects(MachineInstr *MI) const {
324 const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
325 if (!(TID->Flags & M_NEVER_HAS_SIDE_EFFECTS ||
326 TID->Flags & M_MAY_HAVE_SIDE_EFFECTS)) return true;
327 if (TID->Flags & M_NEVER_HAS_SIDE_EFFECTS) return false;
328 return !isReallySideEffectFree(MI); // May have side effects
331 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
332 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the
333 /// instruction itself is actually trivially rematerializable, considering
334 /// its operands. This is used for targets that have instructions that are
335 /// only trivially rematerializable for specific uses. This predicate must
336 /// return false if the instruction has any side effects other than
337 /// producing a value, or if it requres any address registers that are not
338 /// always available.
339 virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const {
343 /// isReallySideEffectFree - If the M_MAY_HAVE_SIDE_EFFECTS flag is set, this
344 /// method is called to determine if the specific instance of this
345 /// instruction has side effects. This is useful in cases of instructions,
346 /// like loads, which generally always have side effects. A load from a
347 /// constant pool doesn't have side effects, though. So we need to
348 /// differentiate it from the general case.
349 virtual bool isReallySideEffectFree(MachineInstr *MI) const {
353 /// getOperandConstraint - Returns the value of the specific constraint if
354 /// it is set. Returns -1 if it is not set.
355 int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum,
356 TOI::OperandConstraint Constraint) const {
357 return get(Opcode).getOperandConstraint(OpNum, Constraint);
360 /// Return true if the instruction is a register to register move
361 /// and leave the source and dest operands in the passed parameters.
362 virtual bool isMoveInstr(const MachineInstr& MI,
364 unsigned& destReg) const {
368 /// isLoadFromStackSlot - If the specified machine instruction is a direct
369 /// load from a stack slot, return the virtual or physical register number of
370 /// the destination along with the FrameIndex of the loaded stack slot. If
371 /// not, return 0. This predicate must return 0 if the instruction has
372 /// any side effects other than loading from the stack slot.
373 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
377 /// isStoreToStackSlot - If the specified machine instruction is a direct
378 /// store to a stack slot, return the virtual or physical register number of
379 /// the source reg along with the FrameIndex of the loaded stack slot. If
380 /// not, return 0. This predicate must return 0 if the instruction has
381 /// any side effects other than storing to the stack slot.
382 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
386 /// convertToThreeAddress - This method must be implemented by targets that
387 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
388 /// may be able to convert a two-address instruction into one or more true
389 /// three-address instructions on demand. This allows the X86 target (for
390 /// example) to convert ADD and SHL instructions into LEA instructions if they
391 /// would require register copies due to two-addressness.
393 /// This method returns a null pointer if the transformation cannot be
394 /// performed, otherwise it returns the last new instruction.
396 virtual MachineInstr *
397 convertToThreeAddress(MachineFunction::iterator &MFI,
398 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const {
402 /// commuteInstruction - If a target has any instructions that are commutable,
403 /// but require converting to a different instruction or making non-trivial
404 /// changes to commute them, this method can overloaded to do this. The
405 /// default implementation of this method simply swaps the first two operands
406 /// of MI and returns it.
408 /// If a target wants to make more aggressive changes, they can construct and
409 /// return a new machine instruction. If an instruction cannot commute, it
410 /// can also return null.
412 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0;
414 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
415 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
416 /// implemented for a target). Upon success, this returns false and returns
417 /// with the following information in various cases:
419 /// 1. If this block ends with no branches (it just falls through to its succ)
420 /// just return false, leaving TBB/FBB null.
421 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
422 /// the destination block.
423 /// 3. If this block ends with an conditional branch and it falls through to
424 /// an successor block, it sets TBB to be the branch destination block and a
425 /// list of operands that evaluate the condition. These
426 /// operands can be passed to other TargetInstrInfo methods to create new
428 /// 4. If this block ends with an conditional branch and an unconditional
429 /// block, it returns the 'true' destination in TBB, the 'false' destination
430 /// in FBB, and a list of operands that evaluate the condition. These
431 /// operands can be passed to other TargetInstrInfo methods to create new
434 /// Note that RemoveBranch and InsertBranch must be implemented to support
435 /// cases where this method returns success.
437 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
438 MachineBasicBlock *&FBB,
439 std::vector<MachineOperand> &Cond) const {
443 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
444 /// this is only invoked in cases where AnalyzeBranch returns success. It
445 /// returns the number of instructions that were removed.
446 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
447 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
451 /// InsertBranch - Insert a branch into the end of the specified
452 /// MachineBasicBlock. This operands to this method are the same as those
453 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
454 /// returns success and when an unconditional branch (TBB is non-null, FBB is
455 /// null, Cond is empty) needs to be inserted. It returns the number of
456 /// instructions inserted.
457 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
458 MachineBasicBlock *FBB,
459 const std::vector<MachineOperand> &Cond) const {
460 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
464 /// copyRegToReg - Add a copy between a pair of registers
465 virtual void copyRegToReg(MachineBasicBlock &MBB,
466 MachineBasicBlock::iterator MI,
467 unsigned DestReg, unsigned SrcReg,
468 const TargetRegisterClass *DestRC,
469 const TargetRegisterClass *SrcRC) const {
470 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
473 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
474 MachineBasicBlock::iterator MI,
475 unsigned SrcReg, bool isKill, int FrameIndex,
476 const TargetRegisterClass *RC) const {
477 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
480 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
481 SmallVectorImpl<MachineOperand> &Addr,
482 const TargetRegisterClass *RC,
483 SmallVectorImpl<MachineInstr*> &NewMIs) const {
484 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!");
487 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
488 MachineBasicBlock::iterator MI,
489 unsigned DestReg, int FrameIndex,
490 const TargetRegisterClass *RC) const {
491 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
494 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
495 SmallVectorImpl<MachineOperand> &Addr,
496 const TargetRegisterClass *RC,
497 SmallVectorImpl<MachineInstr*> &NewMIs) const {
498 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!");
501 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
502 /// saved registers and returns true if it isn't possible / profitable to do
503 /// so by issuing a series of store instructions via
504 /// storeRegToStackSlot(). Returns false otherwise.
505 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
506 MachineBasicBlock::iterator MI,
507 const std::vector<CalleeSavedInfo> &CSI) const {
511 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
512 /// saved registers and returns true if it isn't possible / profitable to do
513 /// so by issuing a series of load instructions via loadRegToStackSlot().
514 /// Returns false otherwise.
515 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
516 MachineBasicBlock::iterator MI,
517 const std::vector<CalleeSavedInfo> &CSI) const {
521 /// BlockHasNoFallThrough - Return true if the specified block does not
522 /// fall-through into its successor block. This is primarily used when a
523 /// branch is unanalyzable. It is useful for things like unconditional
524 /// indirect branches (jump tables).
525 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
529 /// ReverseBranchCondition - Reverses the branch condition of the specified
530 /// condition list, returning false on success and true if it cannot be
532 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
536 /// insertNoop - Insert a noop into the instruction stream at the specified
538 virtual void insertNoop(MachineBasicBlock &MBB,
539 MachineBasicBlock::iterator MI) const {
540 assert(0 && "Target didn't implement insertNoop!");
544 /// isPredicated - Returns true if the instruction is already predicated.
546 virtual bool isPredicated(const MachineInstr *MI) const {
550 /// isUnpredicatedTerminator - Returns true if the instruction is a
551 /// terminator instruction that has not been predicated.
552 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
554 /// PredicateInstruction - Convert the instruction into a predicated
555 /// instruction. It returns true if the operation was successful.
557 bool PredicateInstruction(MachineInstr *MI,
558 const std::vector<MachineOperand> &Pred) const = 0;
560 /// SubsumesPredicate - Returns true if the first specified predicate
561 /// subsumes the second, e.g. GE subsumes GT.
563 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
564 const std::vector<MachineOperand> &Pred2) const {
568 /// DefinesPredicate - If the specified instruction defines any predicate
569 /// or condition code register(s) used for predication, returns true as well
570 /// as the definition predicate(s) by reference.
571 virtual bool DefinesPredicate(MachineInstr *MI,
572 std::vector<MachineOperand> &Pred) const {
576 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
578 virtual const TargetRegisterClass *getPointerRegClass() const {
579 assert(0 && "Target didn't implement getPointerRegClass!");
581 return 0; // Must return a value in order to compile with VS 2005
585 /// TargetInstrInfoImpl - This is the default implementation of
586 /// TargetInstrInfo, which just provides a couple of default implementations
587 /// for various methods. This separated out because it is implemented in
588 /// libcodegen, not in libtarget.
589 class TargetInstrInfoImpl : public TargetInstrInfo {
591 TargetInstrInfoImpl(const TargetInstrDescriptor *desc, unsigned NumOpcodes)
592 : TargetInstrInfo(desc, NumOpcodes) {}
594 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
595 virtual bool PredicateInstruction(MachineInstr *MI,
596 const std::vector<MachineOperand> &Pred) const;
600 } // End llvm namespace