1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/IR/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
25 class SubRegIndex<int size = -1, int offset = 0> {
26 string Namespace = "";
28 // Size - Size (in bits) of the sub-registers represented by this index.
31 // Offset - Offset of the first bit that is part of this sub-register index.
34 // ComposedOf - A list of two SubRegIndex instances, [A, B].
35 // This indicates that this SubRegIndex is the result of composing A and B.
36 // See ComposedSubRegIndex.
37 list<SubRegIndex> ComposedOf = [];
39 // CoveringSubRegIndices - A list of two or more sub-register indexes that
40 // cover this sub-register.
42 // This field should normally be left blank as TableGen can infer it.
44 // TableGen automatically detects sub-registers that straddle the registers
45 // in the SubRegs field of a Register definition. For example:
47 // Q0 = dsub_0 -> D0, dsub_1 -> D1
48 // Q1 = dsub_0 -> D2, dsub_1 -> D3
49 // D1_D2 = dsub_0 -> D1, dsub_1 -> D2
50 // QQ0 = qsub_0 -> Q0, qsub_1 -> Q1
52 // TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given
53 // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with
54 // CoveringSubRegIndices = [dsub_1, dsub_2].
55 list<SubRegIndex> CoveringSubRegIndices = [];
58 // ComposedSubRegIndex - A sub-register that is the result of composing A and B.
59 // Offset is set to the sum of A and B's Offsets. Size is set to B's Size.
60 class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B>
61 : SubRegIndex<B.Size, -1> {
63 let ComposedOf = [A, B];
66 // RegAltNameIndex - The alternate name set to use for register operands of
67 // this register class when printing.
68 class RegAltNameIndex {
69 string Namespace = "";
71 def NoRegAltName : RegAltNameIndex;
73 // Register - You should define one instance of this class for each register
74 // in the target machine. String n will become the "name" of the register.
75 class Register<string n, list<string> altNames = []> {
76 string Namespace = "";
78 list<string> AltNames = altNames;
80 // Aliases - A list of registers that this register overlaps with. A read or
81 // modification of this register can potentially read or modify the aliased
83 list<Register> Aliases = [];
85 // SubRegs - A list of registers that are parts of this register. Note these
86 // are "immediate" sub-registers and the registers within the list do not
87 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
89 list<Register> SubRegs = [];
91 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
92 // to address it. Sub-sub-register indices are automatically inherited from
94 list<SubRegIndex> SubRegIndices = [];
96 // RegAltNameIndices - The alternate name indices which are valid for this
98 list<RegAltNameIndex> RegAltNameIndices = [];
100 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
101 // These values can be determined by locating the <target>.h file in the
102 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
103 // order of these names correspond to the enumeration used by gcc. A value of
104 // -1 indicates that the gcc number is undefined and -2 that register number
105 // is invalid for this mode/flavour.
106 list<int> DwarfNumbers = [];
108 // CostPerUse - Additional cost of instructions using this register compared
109 // to other registers in its class. The register allocator will try to
110 // minimize the number of instructions using a register with a CostPerUse.
111 // This is used by the x86-64 and ARM Thumb targets where some registers
112 // require larger instruction encodings.
115 // CoveredBySubRegs - When this bit is set, the value of this register is
116 // completely determined by the value of its sub-registers. For example, the
117 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not
118 // covered by its sub-register AX.
119 bit CoveredBySubRegs = 0;
121 // HWEncoding - The target specific hardware encoding for this register.
122 bits<16> HWEncoding = 0;
125 // RegisterWithSubRegs - This can be used to define instances of Register which
126 // need to specify sub-registers.
127 // List "subregs" specifies which registers are sub-registers to this one. This
128 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
129 // This allows the code generator to be careful not to put two values with
130 // overlapping live ranges into registers which alias.
131 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
132 let SubRegs = subregs;
135 // DAGOperand - An empty base class that unifies RegisterClass's and other forms
136 // of Operand's that are legal as type qualifiers in DAG patterns. This should
137 // only ever be used for defining multiclasses that are polymorphic over both
138 // RegisterClass's and other Operand's.
141 // RegisterClass - Now that all of the registers are defined, and aliases
142 // between registers are defined, specify which registers belong to which
143 // register classes. This also defines the default allocation order of
144 // registers by register allocators.
146 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
147 dag regList, RegAltNameIndex idx = NoRegAltName>
149 string Namespace = namespace;
151 // RegType - Specify the list ValueType of the registers in this register
152 // class. Note that all registers in a register class must have the same
153 // ValueTypes. This is a list because some targets permit storing different
154 // types in same register, for example vector values with 128-bit total size,
155 // but different count/size of items, like SSE on x86.
157 list<ValueType> RegTypes = regTypes;
159 // Size - Specify the spill size in bits of the registers. A default value of
160 // zero lets tablgen pick an appropriate size.
163 // Alignment - Specify the alignment required of the registers when they are
164 // stored or loaded to memory.
166 int Alignment = alignment;
168 // CopyCost - This value is used to specify the cost of copying a value
169 // between two registers in this register class. The default value is one
170 // meaning it takes a single instruction to perform the copying. A negative
171 // value means copying is extremely expensive or impossible.
174 // MemberList - Specify which registers are in this class. If the
175 // allocation_order_* method are not specified, this also defines the order of
176 // allocation used by the register allocator.
178 dag MemberList = regList;
180 // AltNameIndex - The alternate register name to use when printing operands
181 // of this register class. Every register in the register class must have
182 // a valid alternate name for the given index.
183 RegAltNameIndex altNameIndex = idx;
185 // isAllocatable - Specify that the register class can be used for virtual
186 // registers and register allocation. Some register classes are only used to
187 // model instruction operand constraints, and should have isAllocatable = 0.
188 bit isAllocatable = 1;
190 // AltOrders - List of alternative allocation orders. The default order is
191 // MemberList itself, and that is good enough for most targets since the
192 // register allocators automatically remove reserved registers and move
193 // callee-saved registers to the end.
194 list<dag> AltOrders = [];
196 // AltOrderSelect - The body of a function that selects the allocation order
197 // to use in a given machine function. The code will be inserted in a
198 // function like this:
200 // static inline unsigned f(const MachineFunction &MF) { ... }
202 // The function should return 0 to select the default order defined by
203 // MemberList, 1 to select the first AltOrders entry and so on.
204 code AltOrderSelect = [{}];
207 // The memberList in a RegisterClass is a dag of set operations. TableGen
208 // evaluates these set operations and expand them into register lists. These
209 // are the most common operation, see test/TableGen/SetTheory.td for more
210 // examples of what is possible:
212 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
213 // register class, or a sub-expression. This is also the way to simply list
216 // (sub GPR, SP) - Set difference. Subtract the last arguments from the first.
218 // (and GPR, CSR) - Set intersection. All registers from the first set that are
219 // also in the second set.
221 // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
222 // numbered registers. Takes an optional 4th operand which is a stride to use
223 // when generating the sequence.
225 // (shl GPR, 4) - Remove the first N elements.
227 // (trunc GPR, 4) - Truncate after the first N elements.
229 // (rotl GPR, 1) - Rotate N places to the left.
231 // (rotr GPR, 1) - Rotate N places to the right.
233 // (decimate GPR, 2) - Pick every N'th element, starting with the first.
235 // (interleave A, B, ...) - Interleave the elements from each argument list.
237 // All of these operators work on ordered sets, not lists. That means
238 // duplicates are removed from sub-expressions.
240 // Set operators. The rest is defined in TargetSelectionDAG.td.
245 // RegisterTuples - Automatically generate super-registers by forming tuples of
246 // sub-registers. This is useful for modeling register sequence constraints
247 // with pseudo-registers that are larger than the architectural registers.
249 // The sub-register lists are zipped together:
251 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
253 // Generates the same registers as:
255 // let SubRegIndices = [sube, subo] in {
256 // def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>;
257 // def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>;
260 // The generated pseudo-registers inherit super-classes and fields from their
261 // first sub-register. Most fields from the Register class are inferred, and
262 // the AsmName and Dwarf numbers are cleared.
264 // RegisterTuples instances can be used in other set operations to form
265 // register classes and so on. This is the only way of using the generated
267 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
268 // SubRegs - N lists of registers to be zipped up. Super-registers are
269 // synthesized from the first element of each SubRegs list, the second
270 // element and so on.
271 list<dag> SubRegs = Regs;
273 // SubRegIndices - N SubRegIndex instances. This provides the names of the
274 // sub-registers in the synthesized super-registers.
275 list<SubRegIndex> SubRegIndices = Indices;
279 //===----------------------------------------------------------------------===//
280 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
281 // to the register numbering used by gcc and gdb. These values are used by a
282 // debug information writer to describe where values may be located during
284 class DwarfRegNum<list<int> Numbers> {
285 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
286 // These values can be determined by locating the <target>.h file in the
287 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
288 // order of these names correspond to the enumeration used by gcc. A value of
289 // -1 indicates that the gcc number is undefined and -2 that register number
290 // is invalid for this mode/flavour.
291 list<int> DwarfNumbers = Numbers;
294 // DwarfRegAlias - This class declares that a given register uses the same dwarf
295 // numbers as another one. This is useful for making it clear that the two
296 // registers do have the same number. It also lets us build a mapping
297 // from dwarf register number to llvm register.
298 class DwarfRegAlias<Register reg> {
299 Register DwarfAlias = reg;
302 //===----------------------------------------------------------------------===//
303 // Pull in the common support for scheduling
305 include "llvm/Target/TargetSchedule.td"
307 class Predicate; // Forward def
309 //===----------------------------------------------------------------------===//
310 // Instruction set description - These classes correspond to the C++ classes in
311 // the Target/TargetInstrInfo.h file.
314 string Namespace = "";
316 dag OutOperandList; // An dag containing the MI def operand list.
317 dag InOperandList; // An dag containing the MI use operand list.
318 string AsmString = ""; // The .s format to print the instruction with.
320 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
321 // otherwise, uninitialized.
324 // The follow state will eventually be inferred automatically from the
325 // instruction pattern.
327 list<Register> Uses = []; // Default to using no non-operand registers
328 list<Register> Defs = []; // Default to modifying no non-operand registers
330 // Predicates - List of predicates which will be turned into isel matching
332 list<Predicate> Predicates = [];
334 // Size - Size of encoded instruction, or zero if the size cannot be determined
338 // DecoderNamespace - The "namespace" in which this instruction exists, on
339 // targets like ARM which multiple ISA namespaces exist.
340 string DecoderNamespace = "";
342 // Code size, for instruction selection.
343 // FIXME: What does this actually mean?
346 // Added complexity passed onto matching pattern.
347 int AddedComplexity = 0;
349 // These bits capture information about the high-level semantics of the
351 bit isReturn = 0; // Is this instruction a return instruction?
352 bit isBranch = 0; // Is this instruction a branch instruction?
353 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
354 bit isCompare = 0; // Is this instruction a comparison instruction?
355 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
356 bit isBitcast = 0; // Is this instruction a bitcast instruction?
357 bit isSelect = 0; // Is this instruction a select instruction?
358 bit isBarrier = 0; // Can control flow fall through this instruction?
359 bit isCall = 0; // Is this instruction a call instruction?
360 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
361 bit mayLoad = ?; // Is it possible for this inst to read memory?
362 bit mayStore = ?; // Is it possible for this inst to write memory?
363 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
364 bit isCommutable = 0; // Is this 3 operand instruction commutable?
365 bit isTerminator = 0; // Is this part of the terminator for a basic block?
366 bit isReMaterializable = 0; // Is this instruction re-materializable?
367 bit isPredicable = 0; // Is this instruction predicable?
368 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
369 bit usesCustomInserter = 0; // Pseudo instr needing special help.
370 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
371 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
372 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
373 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
374 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
375 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
376 bit isPseudo = 0; // Is this instruction a pseudo-instruction?
377 // If so, won't have encoding information for
378 // the [MC]CodeEmitter stuff.
380 // Side effect flags - When set, the flags have these meanings:
382 // hasSideEffects - The instruction has side effects that are not
383 // captured by any operands of the instruction or other flags.
385 // neverHasSideEffects (deprecated) - Set on an instruction with no pattern
386 // if it has no side effects. This is now equivalent to setting
387 // "hasSideEffects = 0".
388 bit hasSideEffects = ?;
389 bit neverHasSideEffects = 0;
391 // Is this instruction a "real" instruction (with a distinct machine
392 // encoding), or is it a pseudo instruction used for codegen modeling
394 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only
395 // instructions can (and often do) still have encoding information
396 // associated with them. Once we've migrated all of them over to true
397 // pseudo-instructions that are lowered to real instructions prior to
398 // the printer/emitter, we can remove this attribute and just use isPseudo.
400 // The intended use is:
401 // isPseudo: Does not have encoding information and should be expanded,
402 // at the latest, during lowering to MCInst.
404 // isCodeGenOnly: Does have encoding information and can go through to the
405 // CodeEmitter unchanged, but duplicates a canonical instruction
406 // definition's encoding and should be ignored when constructing the
407 // assembler match tables.
408 bit isCodeGenOnly = 0;
410 // Is this instruction a pseudo instruction for use by the assembler parser.
411 bit isAsmParserOnly = 0;
413 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
415 // Scheduling information from TargetSchedule.td.
416 list<SchedReadWrite> SchedRW;
418 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
420 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
421 /// be encoded into the output machineinstr.
422 string DisableEncoding = "";
424 string PostEncoderMethod = "";
425 string DecoderMethod = "";
427 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
428 bits<64> TSFlags = 0;
430 ///@name Assembler Parser Support
433 string AsmMatchConverter = "";
435 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a
436 /// two-operand matcher inst-alias for a three operand instruction.
437 /// For example, the arm instruction "add r3, r3, r5" can be written
438 /// as "add r3, r5". The constraint is of the same form as a tied-operand
439 /// constraint. For example, "$Rn = $Rd".
440 string TwoOperandAliasConstraint = "";
445 /// PseudoInstExpansion - Expansion information for a pseudo-instruction.
446 /// Which instruction it expands to and how the operands map from the
448 class PseudoInstExpansion<dag Result> {
449 dag ResultInst = Result; // The instruction to generate.
453 /// Predicates - These are extra conditionals which are turned into instruction
454 /// selector matching code. Currently each predicate is just a string.
455 class Predicate<string cond> {
456 string CondString = cond;
458 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
459 /// matcher, this is true. Targets should set this by inheriting their
460 /// feature from the AssemblerPredicate class in addition to Predicate.
461 bit AssemblerMatcherPredicate = 0;
463 /// AssemblerCondString - Name of the subtarget feature being tested used
464 /// as alternative condition string used for assembler matcher.
465 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0".
466 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".
467 /// It can also list multiple features separated by ",".
468 /// e.g. "ModeThumb,FeatureThumb2" is translated to
469 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
470 string AssemblerCondString = "";
472 /// PredicateName - User-level name to use for the predicate. Mainly for use
473 /// in diagnostics such as missing feature errors in the asm matcher.
474 string PredicateName = "";
477 /// NoHonorSignDependentRounding - This predicate is true if support for
478 /// sign-dependent-rounding is not enabled.
479 def NoHonorSignDependentRounding
480 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">;
482 class Requires<list<Predicate> preds> {
483 list<Predicate> Predicates = preds;
486 /// ops definition - This is just a simple marker used to identify the operand
487 /// list for an instruction. outs and ins are identical both syntactically and
488 /// semanticallyr; they are used to define def operands and use operands to
489 /// improve readibility. This should be used like this:
490 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
495 /// variable_ops definition - Mark this instruction as taking a variable number
500 /// PointerLikeRegClass - Values that are designed to have pointer width are
501 /// derived from this. TableGen treats the register class as having a symbolic
502 /// type that it doesn't know, and resolves the actual regclass to use by using
503 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
504 class PointerLikeRegClass<int Kind> {
505 int RegClassKind = Kind;
509 /// ptr_rc definition - Mark this operand as being a pointer value whose
510 /// register class is resolved dynamically via a callback to TargetInstrInfo.
511 /// FIXME: We should probably change this to a class which contain a list of
512 /// flags. But currently we have but one flag.
513 def ptr_rc : PointerLikeRegClass<0>;
515 /// unknown definition - Mark this operand as being of unknown type, causing
516 /// it to be resolved by inference in the context it is used.
518 def unknown : unknown_class;
520 /// AsmOperandClass - Representation for the kinds of operands which the target
521 /// specific parser can create and the assembly matcher may need to distinguish.
523 /// Operand classes are used to define the order in which instructions are
524 /// matched, to ensure that the instruction which gets matched for any
525 /// particular list of operands is deterministic.
527 /// The target specific parser must be able to classify a parsed operand into a
528 /// unique class which does not partially overlap with any other classes. It can
529 /// match a subset of some other class, in which case the super class field
530 /// should be defined.
531 class AsmOperandClass {
532 /// The name to use for this class, which should be usable as an enum value.
535 /// The super classes of this operand.
536 list<AsmOperandClass> SuperClasses = [];
538 /// The name of the method on the target specific operand to call to test
539 /// whether the operand is an instance of this class. If not set, this will
540 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
541 /// signature should be:
542 /// bool isFoo() const;
543 string PredicateMethod = ?;
545 /// The name of the method on the target specific operand to call to add the
546 /// target specific operand to an MCInst. If not set, this will default to
547 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
548 /// signature should be:
549 /// void addFooOperands(MCInst &Inst, unsigned N) const;
550 string RenderMethod = ?;
552 /// The name of the method on the target specific operand to call to custom
553 /// handle the operand parsing. This is useful when the operands do not relate
554 /// to immediates or registers and are very instruction specific (as flags to
555 /// set in a processor register, coprocessor number, ...).
556 string ParserMethod = ?;
558 // The diagnostic type to present when referencing this operand in a
559 // match failure error message. By default, use a generic "invalid operand"
560 // diagnostic. The target AsmParser maps these codes to text.
561 string DiagnosticType = "";
564 def ImmAsmOperand : AsmOperandClass {
568 /// Operand Types - These provide the built-in operand types that may be used
569 /// by a target. Targets can optionally provide their own operand types as
570 /// needed, though this should not be needed for RISC targets.
571 class Operand<ValueType ty> : DAGOperand {
573 string PrintMethod = "printOperand";
574 string EncoderMethod = "";
575 string DecoderMethod = "";
576 string AsmOperandLowerMethod = ?;
577 string OperandType = "OPERAND_UNKNOWN";
578 dag MIOperandInfo = (ops);
580 // ParserMatchClass - The "match class" that operands of this type fit
581 // in. Match classes are used to define the order in which instructions are
582 // match, to ensure that which instructions gets matched is deterministic.
584 // The target specific parser must be able to classify an parsed operand into
585 // a unique class, which does not partially overlap with any other classes. It
586 // can match a subset of some other class, in which case the AsmOperandClass
587 // should declare the other operand as one of its super classes.
588 AsmOperandClass ParserMatchClass = ImmAsmOperand;
591 class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
593 // RegClass - The register class of the operand.
594 RegisterClass RegClass = regclass;
595 // PrintMethod - The target method to call to print register operands of
596 // this type. The method normally will just use an alt-name index to look
597 // up the name to print. Default to the generic printOperand().
598 string PrintMethod = pm;
599 // ParserMatchClass - The "match class" that operands of this type fit
600 // in. Match classes are used to define the order in which instructions are
601 // match, to ensure that which instructions gets matched is deterministic.
603 // The target specific parser must be able to classify an parsed operand into
604 // a unique class, which does not partially overlap with any other classes. It
605 // can match a subset of some other class, in which case the AsmOperandClass
606 // should declare the other operand as one of its super classes.
607 AsmOperandClass ParserMatchClass;
610 let OperandType = "OPERAND_IMMEDIATE" in {
611 def i1imm : Operand<i1>;
612 def i8imm : Operand<i8>;
613 def i16imm : Operand<i16>;
614 def i32imm : Operand<i32>;
615 def i64imm : Operand<i64>;
617 def f32imm : Operand<f32>;
618 def f64imm : Operand<f64>;
621 /// zero_reg definition - Special node to stand for the zero register.
625 /// OperandWithDefaultOps - This Operand class can be used as the parent class
626 /// for an Operand that needs to be initialized with a default value if
627 /// no value is supplied in a pattern. This class can be used to simplify the
628 /// pattern definitions for instructions that have target specific flags
629 /// encoded as immediate operands.
630 class OperandWithDefaultOps<ValueType ty, dag defaultops>
632 dag DefaultOps = defaultops;
635 /// PredicateOperand - This can be used to define a predicate operand for an
636 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
637 /// AlwaysVal specifies the value of this predicate when set to "always
639 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
640 : OperandWithDefaultOps<ty, AlwaysVal> {
641 let MIOperandInfo = OpTypes;
644 /// OptionalDefOperand - This is used to define a optional definition operand
645 /// for an instruction. DefaultOps is the register the operand represents if
646 /// none is supplied, e.g. zero_reg.
647 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
648 : OperandWithDefaultOps<ty, defaultops> {
649 let MIOperandInfo = OpTypes;
653 // InstrInfo - This class should only be instantiated once to provide parameters
654 // which are global to the target machine.
657 // Target can specify its instructions in either big or little-endian formats.
658 // For instance, while both Sparc and PowerPC are big-endian platforms, the
659 // Sparc manual specifies its instructions in the format [31..0] (big), while
660 // PowerPC specifies them using the format [0..31] (little).
661 bit isLittleEndianEncoding = 0;
663 // The instruction properties mayLoad, mayStore, and hasSideEffects are unset
664 // by default, and TableGen will infer their value from the instruction
665 // pattern when possible.
667 // Normally, TableGen will issue an error it it can't infer the value of a
668 // property that hasn't been set explicitly. When guessInstructionProperties
669 // is set, it will guess a safe value instead.
671 // This option is a temporary migration help. It will go away.
672 bit guessInstructionProperties = 1;
675 // Standard Pseudo Instructions.
676 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
677 // Only these instructions are allowed in the TargetOpcode namespace.
678 let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in {
679 def PHI : Instruction {
680 let OutOperandList = (outs);
681 let InOperandList = (ins variable_ops);
682 let AsmString = "PHINODE";
684 def INLINEASM : Instruction {
685 let OutOperandList = (outs);
686 let InOperandList = (ins variable_ops);
688 let neverHasSideEffects = 1; // Note side effect is encoded in an operand.
690 def PROLOG_LABEL : Instruction {
691 let OutOperandList = (outs);
692 let InOperandList = (ins i32imm:$id);
695 let isNotDuplicable = 1;
697 def EH_LABEL : Instruction {
698 let OutOperandList = (outs);
699 let InOperandList = (ins i32imm:$id);
702 let isNotDuplicable = 1;
704 def GC_LABEL : Instruction {
705 let OutOperandList = (outs);
706 let InOperandList = (ins i32imm:$id);
709 let isNotDuplicable = 1;
711 def KILL : Instruction {
712 let OutOperandList = (outs);
713 let InOperandList = (ins variable_ops);
715 let neverHasSideEffects = 1;
717 def EXTRACT_SUBREG : Instruction {
718 let OutOperandList = (outs unknown:$dst);
719 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
721 let neverHasSideEffects = 1;
723 def INSERT_SUBREG : Instruction {
724 let OutOperandList = (outs unknown:$dst);
725 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
727 let neverHasSideEffects = 1;
728 let Constraints = "$supersrc = $dst";
730 def IMPLICIT_DEF : Instruction {
731 let OutOperandList = (outs unknown:$dst);
732 let InOperandList = (ins);
734 let neverHasSideEffects = 1;
735 let isReMaterializable = 1;
736 let isAsCheapAsAMove = 1;
738 def SUBREG_TO_REG : Instruction {
739 let OutOperandList = (outs unknown:$dst);
740 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
742 let neverHasSideEffects = 1;
744 def COPY_TO_REGCLASS : Instruction {
745 let OutOperandList = (outs unknown:$dst);
746 let InOperandList = (ins unknown:$src, i32imm:$regclass);
748 let neverHasSideEffects = 1;
749 let isAsCheapAsAMove = 1;
751 def DBG_VALUE : Instruction {
752 let OutOperandList = (outs);
753 let InOperandList = (ins variable_ops);
754 let AsmString = "DBG_VALUE";
755 let neverHasSideEffects = 1;
757 def REG_SEQUENCE : Instruction {
758 let OutOperandList = (outs unknown:$dst);
759 let InOperandList = (ins variable_ops);
761 let neverHasSideEffects = 1;
762 let isAsCheapAsAMove = 1;
764 def COPY : Instruction {
765 let OutOperandList = (outs unknown:$dst);
766 let InOperandList = (ins unknown:$src);
768 let neverHasSideEffects = 1;
769 let isAsCheapAsAMove = 1;
771 def BUNDLE : Instruction {
772 let OutOperandList = (outs);
773 let InOperandList = (ins variable_ops);
774 let AsmString = "BUNDLE";
776 def LIFETIME_START : Instruction {
777 let OutOperandList = (outs);
778 let InOperandList = (ins i32imm:$id);
779 let AsmString = "LIFETIME_START";
780 let neverHasSideEffects = 1;
782 def LIFETIME_END : Instruction {
783 let OutOperandList = (outs);
784 let InOperandList = (ins i32imm:$id);
785 let AsmString = "LIFETIME_END";
786 let neverHasSideEffects = 1;
790 //===----------------------------------------------------------------------===//
791 // AsmParser - This class can be implemented by targets that wish to implement
794 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
795 // syntax on X86 for example).
798 // AsmParserClassName - This specifies the suffix to use for the asmparser
799 // class. Generated AsmParser classes are always prefixed with the target
801 string AsmParserClassName = "AsmParser";
803 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
804 // function of the AsmParser class to call on every matched instruction.
805 // This can be used to perform target specific instruction post-processing.
806 string AsmParserInstCleanup = "";
808 // ShouldEmitMatchRegisterName - Set to false if the target needs a hand
809 // written register name matcher
810 bit ShouldEmitMatchRegisterName = 1;
812 def DefaultAsmParser : AsmParser;
814 //===----------------------------------------------------------------------===//
815 // AsmParserVariant - Subtargets can have multiple different assembly parsers
816 // (e.g. AT&T vs Intel syntax on X86 for example). This class can be
817 // implemented by targets to describe such variants.
819 class AsmParserVariant {
820 // Variant - AsmParsers can be of multiple different variants. Variants are
821 // used to support targets that need to parser multiple formats for the
822 // assembly language.
825 // Name - The AsmParser variant name (e.g., AT&T vs Intel).
828 // CommentDelimiter - If given, the delimiter string used to recognize
829 // comments which are hard coded in the .td assembler strings for individual
831 string CommentDelimiter = "";
833 // RegisterPrefix - If given, the token prefix which indicates a register
834 // token. This is used by the matcher to automatically recognize hard coded
835 // register tokens as constrained registers, instead of tokens, for the
836 // purposes of matching.
837 string RegisterPrefix = "";
839 def DefaultAsmParserVariant : AsmParserVariant;
841 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
842 /// matches instructions and aliases.
843 class AssemblerPredicate<string cond, string name = ""> {
844 bit AssemblerMatcherPredicate = 1;
845 string AssemblerCondString = cond;
846 string PredicateName = name;
849 /// TokenAlias - This class allows targets to define assembler token
850 /// operand aliases. That is, a token literal operand which is equivalent
851 /// to another, canonical, token literal. For example, ARM allows:
852 /// vmov.u32 s4, #0 -> vmov.i32, #0
853 /// 'u32' is a more specific designator for the 32-bit integer type specifier
854 /// and is legal for any instruction which accepts 'i32' as a datatype suffix.
855 /// def : TokenAlias<".u32", ".i32">;
857 /// This works by marking the match class of 'From' as a subclass of the
858 /// match class of 'To'.
859 class TokenAlias<string From, string To> {
860 string FromToken = From;
864 /// MnemonicAlias - This class allows targets to define assembler mnemonic
865 /// aliases. This should be used when all forms of one mnemonic are accepted
866 /// with a different mnemonic. For example, X86 allows:
867 /// sal %al, 1 -> shl %al, 1
868 /// sal %ax, %cl -> shl %ax, %cl
869 /// sal %eax, %cl -> shl %eax, %cl
870 /// etc. Though "sal" is accepted with many forms, all of them are directly
871 /// translated to a shl, so it can be handled with (in the case of X86, it
872 /// actually has one for each suffix as well):
873 /// def : MnemonicAlias<"sal", "shl">;
875 /// Mnemonic aliases are mapped before any other translation in the match phase,
876 /// and do allow Requires predicates, e.g.:
878 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
879 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
881 /// Mnemonic aliases can also be constrained to specific variants, e.g.:
883 /// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
885 /// If no variant (e.g., "att" or "intel") is specified then the alias is
886 /// applied unconditionally.
887 class MnemonicAlias<string From, string To, string VariantName = ""> {
888 string FromMnemonic = From;
889 string ToMnemonic = To;
890 string AsmVariantName = VariantName;
892 // Predicates - Predicates that must be true for this remapping to happen.
893 list<Predicate> Predicates = [];
896 /// InstAlias - This defines an alternate assembly syntax that is allowed to
897 /// match an instruction that has a different (more canonical) assembly
899 class InstAlias<string Asm, dag Result, bit Emit = 0b1> {
900 string AsmString = Asm; // The .s format to match the instruction with.
901 dag ResultInst = Result; // The MCInst to generate.
902 bit EmitAlias = Emit; // Emit the alias instead of what's aliased.
904 // Predicates - Predicates that must be true for this to match.
905 list<Predicate> Predicates = [];
908 //===----------------------------------------------------------------------===//
909 // AsmWriter - This class can be implemented by targets that need to customize
910 // the format of the .s file writer.
912 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
913 // on X86 for example).
916 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
917 // class. Generated AsmWriter classes are always prefixed with the target
919 string AsmWriterClassName = "AsmPrinter";
921 // Variant - AsmWriters can be of multiple different variants. Variants are
922 // used to support targets that need to emit assembly code in ways that are
923 // mostly the same for different targets, but have minor differences in
924 // syntax. If the asmstring contains {|} characters in them, this integer
925 // will specify which alternative to use. For example "{x|y|z}" with Variant
926 // == 1, will expand to "y".
930 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar
931 // layout, the asmwriter can actually generate output in this columns (in
932 // verbose-asm mode). These two values indicate the width of the first column
933 // (the "opcode" area) and the width to reserve for subsequent operands. When
934 // verbose asm mode is enabled, operands will be indented to respect this.
935 int FirstOperandColumn = -1;
937 // OperandSpacing - Space between operand columns.
938 int OperandSpacing = -1;
940 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls
941 // generation of the printInstruction() method. For MC printers, it takes
942 // an MCInstr* operand, otherwise it takes a MachineInstr*.
943 bit isMCAsmWriter = 0;
945 def DefaultAsmWriter : AsmWriter;
948 //===----------------------------------------------------------------------===//
949 // Target - This class contains the "global" target information
952 // InstructionSet - Instruction set description for this target.
953 InstrInfo InstructionSet;
955 // AssemblyParsers - The AsmParser instances available for this target.
956 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
958 /// AssemblyParserVariants - The AsmParserVariant instances available for
960 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant];
962 // AssemblyWriters - The AsmWriter instances available for this target.
963 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
966 //===----------------------------------------------------------------------===//
967 // SubtargetFeature - A characteristic of the chip set.
969 class SubtargetFeature<string n, string a, string v, string d,
970 list<SubtargetFeature> i = []> {
971 // Name - Feature name. Used by command line (-mattr=) to determine the
972 // appropriate target chip.
976 // Attribute - Attribute to be set by feature.
978 string Attribute = a;
980 // Value - Value the attribute to be set to by feature.
984 // Desc - Feature description. Used by command line (-mattr=) to display help
989 // Implies - Features that this feature implies are present. If one of those
990 // features isn't set, then this one shouldn't be set either.
992 list<SubtargetFeature> Implies = i;
995 //===----------------------------------------------------------------------===//
996 // Processor chip sets - These values represent each of the chip sets supported
997 // by the scheduler. Each Processor definition requires corresponding
998 // instruction itineraries.
1000 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
1001 // Name - Chip set name. Used by command line (-mcpu=) to determine the
1002 // appropriate target chip.
1006 // SchedModel - The machine model for scheduling and instruction cost.
1008 SchedMachineModel SchedModel = NoSchedModel;
1010 // ProcItin - The scheduling information for the target processor.
1012 ProcessorItineraries ProcItin = pi;
1014 // Features - list of
1015 list<SubtargetFeature> Features = f;
1018 // ProcessorModel allows subtargets to specify the more general
1019 // SchedMachineModel instead if a ProcessorItinerary. Subtargets will
1020 // gradually move to this newer form.
1022 // Although this class always passes NoItineraries to the Processor
1023 // class, the SchedMachineModel may still define valid Itineraries.
1024 class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f>
1025 : Processor<n, NoItineraries, f> {
1029 //===----------------------------------------------------------------------===//
1030 // InstrMapping - This class is used to create mapping tables to relate
1031 // instructions with each other based on the values specified in RowFields,
1032 // ColFields, KeyCol and ValueCols.
1034 class InstrMapping {
1035 // FilterClass - Used to limit search space only to the instructions that
1036 // define the relationship modeled by this InstrMapping record.
1039 // RowFields - List of fields/attributes that should be same for all the
1040 // instructions in a row of the relation table. Think of this as a set of
1041 // properties shared by all the instructions related by this relationship
1042 // model and is used to categorize instructions into subgroups. For instance,
1043 // if we want to define a relation that maps 'Add' instruction to its
1044 // predicated forms, we can define RowFields like this:
1046 // let RowFields = BaseOp
1047 // All add instruction predicated/non-predicated will have to set their BaseOp
1048 // to the same value.
1050 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' }
1051 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' }
1052 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' }
1053 list<string> RowFields = [];
1055 // List of fields/attributes that are same for all the instructions
1056 // in a column of the relation table.
1057 // Ex: let ColFields = 'predSense' -- It means that the columns are arranged
1058 // based on the 'predSense' values. All the instruction in a specific
1059 // column have the same value and it is fixed for the column according
1060 // to the values set in 'ValueCols'.
1061 list<string> ColFields = [];
1063 // Values for the fields/attributes listed in 'ColFields'.
1064 // Ex: let KeyCol = 'nopred' -- It means that the key instruction (instruction
1065 // that models this relation) should be non-predicated.
1066 // In the example above, 'Add' is the key instruction.
1067 list<string> KeyCol = [];
1069 // List of values for the fields/attributes listed in 'ColFields', one for
1070 // each column in the relation table.
1072 // Ex: let ValueCols = [['true'],['false']] -- It adds two columns in the
1073 // table. First column requires all the instructions to have predSense
1074 // set to 'true' and second column requires it to be 'false'.
1075 list<list<string> > ValueCols = [];
1078 //===----------------------------------------------------------------------===//
1079 // Pull in the common support for calling conventions.
1081 include "llvm/Target/TargetCallingConv.td"
1083 //===----------------------------------------------------------------------===//
1084 // Pull in the common support for DAG isel generation.
1086 include "llvm/Target/TargetSelectionDAG.td"