1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
25 class SubRegIndex<list<SubRegIndex> comps = []> {
26 string Namespace = "";
28 // ComposedOf - A list of two SubRegIndex instances, [A, B].
29 // This indicates that this SubRegIndex is the result of composing A and B.
30 list<SubRegIndex> ComposedOf = comps;
33 // RegAltNameIndex - The alternate name set to use for register operands of
34 // this register class when printing.
35 class RegAltNameIndex {
36 string Namespace = "";
38 def NoRegAltName : RegAltNameIndex;
40 // Register - You should define one instance of this class for each register
41 // in the target machine. String n will become the "name" of the register.
42 class Register<string n, list<string> altNames = []> {
43 string Namespace = "";
45 list<string> AltNames = altNames;
47 // Aliases - A list of registers that this register overlaps with. A read or
48 // modification of this register can potentially read or modify the aliased
50 list<Register> Aliases = [];
52 // SubRegs - A list of registers that are parts of this register. Note these
53 // are "immediate" sub-registers and the registers within the list do not
54 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
56 list<Register> SubRegs = [];
58 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
59 // to address it. Sub-sub-register indices are automatically inherited from
61 list<SubRegIndex> SubRegIndices = [];
63 // RegAltNameIndices - The alternate name indices which are valid for this
65 list<RegAltNameIndex> RegAltNameIndices = [];
67 // CompositeIndices - Specify subreg indices that don't correspond directly to
68 // a register in SubRegs and are not inherited. The following formats are
71 // (a) Identity - Reg:a == Reg
72 // (a b) Alias - Reg:a == Reg:b
73 // (a b,c) Composite - Reg:a == (Reg:b):c
75 // This can be used to disambiguate a sub-sub-register that exists in more
76 // than one subregister and other weird stuff.
77 list<dag> CompositeIndices = [];
79 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
80 // These values can be determined by locating the <target>.h file in the
81 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
82 // order of these names correspond to the enumeration used by gcc. A value of
83 // -1 indicates that the gcc number is undefined and -2 that register number
84 // is invalid for this mode/flavour.
85 list<int> DwarfNumbers = [];
87 // CostPerUse - Additional cost of instructions using this register compared
88 // to other registers in its class. The register allocator will try to
89 // minimize the number of instructions using a register with a CostPerUse.
90 // This is used by the x86-64 and ARM Thumb targets where some registers
91 // require larger instruction encodings.
94 // CoveredBySubRegs - When this bit is set, the value of this register is
95 // completely determined by the value of its sub-registers. For example, the
96 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not
97 // covered by its sub-register AX.
98 bit CoveredBySubRegs = 0;
100 // HWEncoding - The target specific hardware encoding for this register.
101 bits<16> HWEncoding = 0;
104 // RegisterWithSubRegs - This can be used to define instances of Register which
105 // need to specify sub-registers.
106 // List "subregs" specifies which registers are sub-registers to this one. This
107 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
108 // This allows the code generator to be careful not to put two values with
109 // overlapping live ranges into registers which alias.
110 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
111 let SubRegs = subregs;
114 // RegisterClass - Now that all of the registers are defined, and aliases
115 // between registers are defined, specify which registers belong to which
116 // register classes. This also defines the default allocation order of
117 // registers by register allocators.
119 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
120 dag regList, RegAltNameIndex idx = NoRegAltName> {
121 string Namespace = namespace;
123 // RegType - Specify the list ValueType of the registers in this register
124 // class. Note that all registers in a register class must have the same
125 // ValueTypes. This is a list because some targets permit storing different
126 // types in same register, for example vector values with 128-bit total size,
127 // but different count/size of items, like SSE on x86.
129 list<ValueType> RegTypes = regTypes;
131 // Size - Specify the spill size in bits of the registers. A default value of
132 // zero lets tablgen pick an appropriate size.
135 // Alignment - Specify the alignment required of the registers when they are
136 // stored or loaded to memory.
138 int Alignment = alignment;
140 // CopyCost - This value is used to specify the cost of copying a value
141 // between two registers in this register class. The default value is one
142 // meaning it takes a single instruction to perform the copying. A negative
143 // value means copying is extremely expensive or impossible.
146 // MemberList - Specify which registers are in this class. If the
147 // allocation_order_* method are not specified, this also defines the order of
148 // allocation used by the register allocator.
150 dag MemberList = regList;
152 // AltNameIndex - The alternate register name to use when printing operands
153 // of this register class. Every register in the register class must have
154 // a valid alternate name for the given index.
155 RegAltNameIndex altNameIndex = idx;
157 // isAllocatable - Specify that the register class can be used for virtual
158 // registers and register allocation. Some register classes are only used to
159 // model instruction operand constraints, and should have isAllocatable = 0.
160 bit isAllocatable = 1;
162 // AltOrders - List of alternative allocation orders. The default order is
163 // MemberList itself, and that is good enough for most targets since the
164 // register allocators automatically remove reserved registers and move
165 // callee-saved registers to the end.
166 list<dag> AltOrders = [];
168 // AltOrderSelect - The body of a function that selects the allocation order
169 // to use in a given machine function. The code will be inserted in a
170 // function like this:
172 // static inline unsigned f(const MachineFunction &MF) { ... }
174 // The function should return 0 to select the default order defined by
175 // MemberList, 1 to select the first AltOrders entry and so on.
176 code AltOrderSelect = [{}];
179 // The memberList in a RegisterClass is a dag of set operations. TableGen
180 // evaluates these set operations and expand them into register lists. These
181 // are the most common operation, see test/TableGen/SetTheory.td for more
182 // examples of what is possible:
184 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
185 // register class, or a sub-expression. This is also the way to simply list
188 // (sub GPR, SP) - Set difference. Subtract the last arguments from the first.
190 // (and GPR, CSR) - Set intersection. All registers from the first set that are
191 // also in the second set.
193 // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
194 // numbered registers.
196 // (shl GPR, 4) - Remove the first N elements.
198 // (trunc GPR, 4) - Truncate after the first N elements.
200 // (rotl GPR, 1) - Rotate N places to the left.
202 // (rotr GPR, 1) - Rotate N places to the right.
204 // (decimate GPR, 2) - Pick every N'th element, starting with the first.
206 // (interleave A, B, ...) - Interleave the elements from each argument list.
208 // All of these operators work on ordered sets, not lists. That means
209 // duplicates are removed from sub-expressions.
211 // Set operators. The rest is defined in TargetSelectionDAG.td.
216 // RegisterTuples - Automatically generate super-registers by forming tuples of
217 // sub-registers. This is useful for modeling register sequence constraints
218 // with pseudo-registers that are larger than the architectural registers.
220 // The sub-register lists are zipped together:
222 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
224 // Generates the same registers as:
226 // let SubRegIndices = [sube, subo] in {
227 // def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>;
228 // def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>;
231 // The generated pseudo-registers inherit super-classes and fields from their
232 // first sub-register. Most fields from the Register class are inferred, and
233 // the AsmName and Dwarf numbers are cleared.
235 // RegisterTuples instances can be used in other set operations to form
236 // register classes and so on. This is the only way of using the generated
238 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
239 // SubRegs - N lists of registers to be zipped up. Super-registers are
240 // synthesized from the first element of each SubRegs list, the second
241 // element and so on.
242 list<dag> SubRegs = Regs;
244 // SubRegIndices - N SubRegIndex instances. This provides the names of the
245 // sub-registers in the synthesized super-registers.
246 list<SubRegIndex> SubRegIndices = Indices;
248 // Compose sub-register indices like in a normal Register.
249 list<dag> CompositeIndices = [];
253 //===----------------------------------------------------------------------===//
254 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
255 // to the register numbering used by gcc and gdb. These values are used by a
256 // debug information writer to describe where values may be located during
258 class DwarfRegNum<list<int> Numbers> {
259 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
260 // These values can be determined by locating the <target>.h file in the
261 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
262 // order of these names correspond to the enumeration used by gcc. A value of
263 // -1 indicates that the gcc number is undefined and -2 that register number
264 // is invalid for this mode/flavour.
265 list<int> DwarfNumbers = Numbers;
268 // DwarfRegAlias - This class declares that a given register uses the same dwarf
269 // numbers as another one. This is useful for making it clear that the two
270 // registers do have the same number. It also lets us build a mapping
271 // from dwarf register number to llvm register.
272 class DwarfRegAlias<Register reg> {
273 Register DwarfAlias = reg;
276 //===----------------------------------------------------------------------===//
277 // Pull in the common support for scheduling
279 include "llvm/Target/TargetSchedule.td"
281 class Predicate; // Forward def
283 //===----------------------------------------------------------------------===//
284 // Instruction set description - These classes correspond to the C++ classes in
285 // the Target/TargetInstrInfo.h file.
288 string Namespace = "";
290 dag OutOperandList; // An dag containing the MI def operand list.
291 dag InOperandList; // An dag containing the MI use operand list.
292 string AsmString = ""; // The .s format to print the instruction with.
294 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
295 // otherwise, uninitialized.
298 // The follow state will eventually be inferred automatically from the
299 // instruction pattern.
301 list<Register> Uses = []; // Default to using no non-operand registers
302 list<Register> Defs = []; // Default to modifying no non-operand registers
304 // Predicates - List of predicates which will be turned into isel matching
306 list<Predicate> Predicates = [];
308 // Size - Size of encoded instruction, or zero if the size cannot be determined
312 // DecoderNamespace - The "namespace" in which this instruction exists, on
313 // targets like ARM which multiple ISA namespaces exist.
314 string DecoderNamespace = "";
316 // Code size, for instruction selection.
317 // FIXME: What does this actually mean?
320 // Added complexity passed onto matching pattern.
321 int AddedComplexity = 0;
323 // These bits capture information about the high-level semantics of the
325 bit isReturn = 0; // Is this instruction a return instruction?
326 bit isBranch = 0; // Is this instruction a branch instruction?
327 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
328 bit isCompare = 0; // Is this instruction a comparison instruction?
329 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
330 bit isBitcast = 0; // Is this instruction a bitcast instruction?
331 bit isBarrier = 0; // Can control flow fall through this instruction?
332 bit isCall = 0; // Is this instruction a call instruction?
333 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
334 bit mayLoad = 0; // Is it possible for this inst to read memory?
335 bit mayStore = 0; // Is it possible for this inst to write memory?
336 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
337 bit isCommutable = 0; // Is this 3 operand instruction commutable?
338 bit isTerminator = 0; // Is this part of the terminator for a basic block?
339 bit isReMaterializable = 0; // Is this instruction re-materializable?
340 bit isPredicable = 0; // Is this instruction predicable?
341 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
342 bit usesCustomInserter = 0; // Pseudo instr needing special help.
343 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
344 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
345 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
346 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
347 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
348 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
349 bit isPseudo = 0; // Is this instruction a pseudo-instruction?
350 // If so, won't have encoding information for
351 // the [MC]CodeEmitter stuff.
353 // Side effect flags - When set, the flags have these meanings:
355 // hasSideEffects - The instruction has side effects that are not
356 // captured by any operands of the instruction or other flags.
358 // neverHasSideEffects - Set on an instruction with no pattern if it has no
360 bit hasSideEffects = 0;
361 bit neverHasSideEffects = 0;
363 // Is this instruction a "real" instruction (with a distinct machine
364 // encoding), or is it a pseudo instruction used for codegen modeling
366 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only
367 // instructions can (and often do) still have encoding information
368 // associated with them. Once we've migrated all of them over to true
369 // pseudo-instructions that are lowered to real instructions prior to
370 // the printer/emitter, we can remove this attribute and just use isPseudo.
372 // The intended use is:
373 // isPseudo: Does not have encoding information and should be expanded,
374 // at the latest, during lowering to MCInst.
376 // isCodeGenOnly: Does have encoding information and can go through to the
377 // CodeEmitter unchanged, but duplicates a canonical instruction
378 // definition's encoding and should be ignored when constructing the
379 // assembler match tables.
380 bit isCodeGenOnly = 0;
382 // Is this instruction a pseudo instruction for use by the assembler parser.
383 bit isAsmParserOnly = 0;
385 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
387 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
389 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
390 /// be encoded into the output machineinstr.
391 string DisableEncoding = "";
393 string PostEncoderMethod = "";
394 string DecoderMethod = "";
396 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
397 bits<64> TSFlags = 0;
399 ///@name Assembler Parser Support
402 string AsmMatchConverter = "";
404 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a
405 /// two-operand matcher inst-alias for a three operand instruction.
406 /// For example, the arm instruction "add r3, r3, r5" can be written
407 /// as "add r3, r5". The constraint is of the same form as a tied-operand
408 /// constraint. For example, "$Rn = $Rd".
409 string TwoOperandAliasConstraint = "";
414 /// PseudoInstExpansion - Expansion information for a pseudo-instruction.
415 /// Which instruction it expands to and how the operands map from the
417 class PseudoInstExpansion<dag Result> {
418 dag ResultInst = Result; // The instruction to generate.
422 /// Predicates - These are extra conditionals which are turned into instruction
423 /// selector matching code. Currently each predicate is just a string.
424 class Predicate<string cond> {
425 string CondString = cond;
427 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
428 /// matcher, this is true. Targets should set this by inheriting their
429 /// feature from the AssemblerPredicate class in addition to Predicate.
430 bit AssemblerMatcherPredicate = 0;
432 /// AssemblerCondString - Name of the subtarget feature being tested used
433 /// as alternative condition string used for assembler matcher.
434 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0".
435 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".
436 /// It can also list multiple features separated by ",".
437 /// e.g. "ModeThumb,FeatureThumb2" is translated to
438 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
439 string AssemblerCondString = "";
441 /// PredicateName - User-level name to use for the predicate. Mainly for use
442 /// in diagnostics such as missing feature errors in the asm matcher.
443 string PredicateName = "";
446 /// NoHonorSignDependentRounding - This predicate is true if support for
447 /// sign-dependent-rounding is not enabled.
448 def NoHonorSignDependentRounding
449 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">;
451 class Requires<list<Predicate> preds> {
452 list<Predicate> Predicates = preds;
455 /// ops definition - This is just a simple marker used to identify the operand
456 /// list for an instruction. outs and ins are identical both syntactically and
457 /// semanticallyr; they are used to define def operands and use operands to
458 /// improve readibility. This should be used like this:
459 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
464 /// variable_ops definition - Mark this instruction as taking a variable number
469 /// PointerLikeRegClass - Values that are designed to have pointer width are
470 /// derived from this. TableGen treats the register class as having a symbolic
471 /// type that it doesn't know, and resolves the actual regclass to use by using
472 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
473 class PointerLikeRegClass<int Kind> {
474 int RegClassKind = Kind;
478 /// ptr_rc definition - Mark this operand as being a pointer value whose
479 /// register class is resolved dynamically via a callback to TargetInstrInfo.
480 /// FIXME: We should probably change this to a class which contain a list of
481 /// flags. But currently we have but one flag.
482 def ptr_rc : PointerLikeRegClass<0>;
484 /// unknown definition - Mark this operand as being of unknown type, causing
485 /// it to be resolved by inference in the context it is used.
488 /// AsmOperandClass - Representation for the kinds of operands which the target
489 /// specific parser can create and the assembly matcher may need to distinguish.
491 /// Operand classes are used to define the order in which instructions are
492 /// matched, to ensure that the instruction which gets matched for any
493 /// particular list of operands is deterministic.
495 /// The target specific parser must be able to classify a parsed operand into a
496 /// unique class which does not partially overlap with any other classes. It can
497 /// match a subset of some other class, in which case the super class field
498 /// should be defined.
499 class AsmOperandClass {
500 /// The name to use for this class, which should be usable as an enum value.
503 /// The super classes of this operand.
504 list<AsmOperandClass> SuperClasses = [];
506 /// The name of the method on the target specific operand to call to test
507 /// whether the operand is an instance of this class. If not set, this will
508 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
509 /// signature should be:
510 /// bool isFoo() const;
511 string PredicateMethod = ?;
513 /// The name of the method on the target specific operand to call to add the
514 /// target specific operand to an MCInst. If not set, this will default to
515 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
516 /// signature should be:
517 /// void addFooOperands(MCInst &Inst, unsigned N) const;
518 string RenderMethod = ?;
520 /// The name of the method on the target specific operand to call to custom
521 /// handle the operand parsing. This is useful when the operands do not relate
522 /// to immediates or registers and are very instruction specific (as flags to
523 /// set in a processor register, coprocessor number, ...).
524 string ParserMethod = ?;
527 def ImmAsmOperand : AsmOperandClass {
531 /// Operand Types - These provide the built-in operand types that may be used
532 /// by a target. Targets can optionally provide their own operand types as
533 /// needed, though this should not be needed for RISC targets.
534 class Operand<ValueType ty> {
536 string PrintMethod = "printOperand";
537 string EncoderMethod = "";
538 string DecoderMethod = "";
539 string AsmOperandLowerMethod = ?;
540 string OperandType = "OPERAND_UNKNOWN";
541 dag MIOperandInfo = (ops);
543 // ParserMatchClass - The "match class" that operands of this type fit
544 // in. Match classes are used to define the order in which instructions are
545 // match, to ensure that which instructions gets matched is deterministic.
547 // The target specific parser must be able to classify an parsed operand into
548 // a unique class, which does not partially overlap with any other classes. It
549 // can match a subset of some other class, in which case the AsmOperandClass
550 // should declare the other operand as one of its super classes.
551 AsmOperandClass ParserMatchClass = ImmAsmOperand;
554 class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> {
555 // RegClass - The register class of the operand.
556 RegisterClass RegClass = regclass;
557 // PrintMethod - The target method to call to print register operands of
558 // this type. The method normally will just use an alt-name index to look
559 // up the name to print. Default to the generic printOperand().
560 string PrintMethod = pm;
561 // ParserMatchClass - The "match class" that operands of this type fit
562 // in. Match classes are used to define the order in which instructions are
563 // match, to ensure that which instructions gets matched is deterministic.
565 // The target specific parser must be able to classify an parsed operand into
566 // a unique class, which does not partially overlap with any other classes. It
567 // can match a subset of some other class, in which case the AsmOperandClass
568 // should declare the other operand as one of its super classes.
569 AsmOperandClass ParserMatchClass;
572 let OperandType = "OPERAND_IMMEDIATE" in {
573 def i1imm : Operand<i1>;
574 def i8imm : Operand<i8>;
575 def i16imm : Operand<i16>;
576 def i32imm : Operand<i32>;
577 def i64imm : Operand<i64>;
579 def f32imm : Operand<f32>;
580 def f64imm : Operand<f64>;
583 /// zero_reg definition - Special node to stand for the zero register.
587 /// PredicateOperand - This can be used to define a predicate operand for an
588 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
589 /// AlwaysVal specifies the value of this predicate when set to "always
591 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
593 let MIOperandInfo = OpTypes;
594 dag DefaultOps = AlwaysVal;
597 /// OptionalDefOperand - This is used to define a optional definition operand
598 /// for an instruction. DefaultOps is the register the operand represents if
599 /// none is supplied, e.g. zero_reg.
600 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
602 let MIOperandInfo = OpTypes;
603 dag DefaultOps = defaultops;
607 // InstrInfo - This class should only be instantiated once to provide parameters
608 // which are global to the target machine.
611 // Target can specify its instructions in either big or little-endian formats.
612 // For instance, while both Sparc and PowerPC are big-endian platforms, the
613 // Sparc manual specifies its instructions in the format [31..0] (big), while
614 // PowerPC specifies them using the format [0..31] (little).
615 bit isLittleEndianEncoding = 0;
618 // Standard Pseudo Instructions.
619 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
620 // Only these instructions are allowed in the TargetOpcode namespace.
621 let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in {
622 def PHI : Instruction {
623 let OutOperandList = (outs);
624 let InOperandList = (ins variable_ops);
625 let AsmString = "PHINODE";
627 def INLINEASM : Instruction {
628 let OutOperandList = (outs);
629 let InOperandList = (ins variable_ops);
631 let neverHasSideEffects = 1; // Note side effect is encoded in an operand.
633 def PROLOG_LABEL : Instruction {
634 let OutOperandList = (outs);
635 let InOperandList = (ins i32imm:$id);
638 let isNotDuplicable = 1;
640 def EH_LABEL : Instruction {
641 let OutOperandList = (outs);
642 let InOperandList = (ins i32imm:$id);
645 let isNotDuplicable = 1;
647 def GC_LABEL : Instruction {
648 let OutOperandList = (outs);
649 let InOperandList = (ins i32imm:$id);
652 let isNotDuplicable = 1;
654 def KILL : Instruction {
655 let OutOperandList = (outs);
656 let InOperandList = (ins variable_ops);
658 let neverHasSideEffects = 1;
660 def EXTRACT_SUBREG : Instruction {
661 let OutOperandList = (outs unknown:$dst);
662 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
664 let neverHasSideEffects = 1;
666 def INSERT_SUBREG : Instruction {
667 let OutOperandList = (outs unknown:$dst);
668 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
670 let neverHasSideEffects = 1;
671 let Constraints = "$supersrc = $dst";
673 def IMPLICIT_DEF : Instruction {
674 let OutOperandList = (outs unknown:$dst);
675 let InOperandList = (ins);
677 let neverHasSideEffects = 1;
678 let isReMaterializable = 1;
679 let isAsCheapAsAMove = 1;
681 def SUBREG_TO_REG : Instruction {
682 let OutOperandList = (outs unknown:$dst);
683 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
685 let neverHasSideEffects = 1;
687 def COPY_TO_REGCLASS : Instruction {
688 let OutOperandList = (outs unknown:$dst);
689 let InOperandList = (ins unknown:$src, i32imm:$regclass);
691 let neverHasSideEffects = 1;
692 let isAsCheapAsAMove = 1;
694 def DBG_VALUE : Instruction {
695 let OutOperandList = (outs);
696 let InOperandList = (ins variable_ops);
697 let AsmString = "DBG_VALUE";
698 let neverHasSideEffects = 1;
700 def REG_SEQUENCE : Instruction {
701 let OutOperandList = (outs unknown:$dst);
702 let InOperandList = (ins variable_ops);
704 let neverHasSideEffects = 1;
705 let isAsCheapAsAMove = 1;
707 def COPY : Instruction {
708 let OutOperandList = (outs unknown:$dst);
709 let InOperandList = (ins unknown:$src);
711 let neverHasSideEffects = 1;
712 let isAsCheapAsAMove = 1;
714 def BUNDLE : Instruction {
715 let OutOperandList = (outs);
716 let InOperandList = (ins variable_ops);
717 let AsmString = "BUNDLE";
721 //===----------------------------------------------------------------------===//
722 // AsmParser - This class can be implemented by targets that wish to implement
725 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
726 // syntax on X86 for example).
729 // AsmParserClassName - This specifies the suffix to use for the asmparser
730 // class. Generated AsmParser classes are always prefixed with the target
732 string AsmParserClassName = "AsmParser";
734 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
735 // function of the AsmParser class to call on every matched instruction.
736 // This can be used to perform target specific instruction post-processing.
737 string AsmParserInstCleanup = "";
739 def DefaultAsmParser : AsmParser;
741 //===----------------------------------------------------------------------===//
742 // AsmParserVariant - Subtargets can have multiple different assembly parsers
743 // (e.g. AT&T vs Intel syntax on X86 for example). This class can be
744 // implemented by targets to describe such variants.
746 class AsmParserVariant {
747 // Variant - AsmParsers can be of multiple different variants. Variants are
748 // used to support targets that need to parser multiple formats for the
749 // assembly language.
752 // CommentDelimiter - If given, the delimiter string used to recognize
753 // comments which are hard coded in the .td assembler strings for individual
755 string CommentDelimiter = "";
757 // RegisterPrefix - If given, the token prefix which indicates a register
758 // token. This is used by the matcher to automatically recognize hard coded
759 // register tokens as constrained registers, instead of tokens, for the
760 // purposes of matching.
761 string RegisterPrefix = "";
763 def DefaultAsmParserVariant : AsmParserVariant;
765 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
766 /// matches instructions and aliases.
767 class AssemblerPredicate<string cond, string name = ""> {
768 bit AssemblerMatcherPredicate = 1;
769 string AssemblerCondString = cond;
770 string PredicateName = name;
773 /// TokenAlias - This class allows targets to define assembler token
774 /// operand aliases. That is, a token literal operand which is equivalent
775 /// to another, canonical, token literal. For example, ARM allows:
776 /// vmov.u32 s4, #0 -> vmov.i32, #0
777 /// 'u32' is a more specific designator for the 32-bit integer type specifier
778 /// and is legal for any instruction which accepts 'i32' as a datatype suffix.
779 /// def : TokenAlias<".u32", ".i32">;
781 /// This works by marking the match class of 'From' as a subclass of the
782 /// match class of 'To'.
783 class TokenAlias<string From, string To> {
784 string FromToken = From;
788 /// MnemonicAlias - This class allows targets to define assembler mnemonic
789 /// aliases. This should be used when all forms of one mnemonic are accepted
790 /// with a different mnemonic. For example, X86 allows:
791 /// sal %al, 1 -> shl %al, 1
792 /// sal %ax, %cl -> shl %ax, %cl
793 /// sal %eax, %cl -> shl %eax, %cl
794 /// etc. Though "sal" is accepted with many forms, all of them are directly
795 /// translated to a shl, so it can be handled with (in the case of X86, it
796 /// actually has one for each suffix as well):
797 /// def : MnemonicAlias<"sal", "shl">;
799 /// Mnemonic aliases are mapped before any other translation in the match phase,
800 /// and do allow Requires predicates, e.g.:
802 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
803 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
805 class MnemonicAlias<string From, string To> {
806 string FromMnemonic = From;
807 string ToMnemonic = To;
809 // Predicates - Predicates that must be true for this remapping to happen.
810 list<Predicate> Predicates = [];
813 /// InstAlias - This defines an alternate assembly syntax that is allowed to
814 /// match an instruction that has a different (more canonical) assembly
816 class InstAlias<string Asm, dag Result, bit Emit = 0b1> {
817 string AsmString = Asm; // The .s format to match the instruction with.
818 dag ResultInst = Result; // The MCInst to generate.
819 bit EmitAlias = Emit; // Emit the alias instead of what's aliased.
821 // Predicates - Predicates that must be true for this to match.
822 list<Predicate> Predicates = [];
825 //===----------------------------------------------------------------------===//
826 // AsmWriter - This class can be implemented by targets that need to customize
827 // the format of the .s file writer.
829 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
830 // on X86 for example).
833 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
834 // class. Generated AsmWriter classes are always prefixed with the target
836 string AsmWriterClassName = "AsmPrinter";
838 // Variant - AsmWriters can be of multiple different variants. Variants are
839 // used to support targets that need to emit assembly code in ways that are
840 // mostly the same for different targets, but have minor differences in
841 // syntax. If the asmstring contains {|} characters in them, this integer
842 // will specify which alternative to use. For example "{x|y|z}" with Variant
843 // == 1, will expand to "y".
847 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar
848 // layout, the asmwriter can actually generate output in this columns (in
849 // verbose-asm mode). These two values indicate the width of the first column
850 // (the "opcode" area) and the width to reserve for subsequent operands. When
851 // verbose asm mode is enabled, operands will be indented to respect this.
852 int FirstOperandColumn = -1;
854 // OperandSpacing - Space between operand columns.
855 int OperandSpacing = -1;
857 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls
858 // generation of the printInstruction() method. For MC printers, it takes
859 // an MCInstr* operand, otherwise it takes a MachineInstr*.
860 bit isMCAsmWriter = 0;
862 def DefaultAsmWriter : AsmWriter;
865 //===----------------------------------------------------------------------===//
866 // Target - This class contains the "global" target information
869 // InstructionSet - Instruction set description for this target.
870 InstrInfo InstructionSet;
872 // AssemblyParsers - The AsmParser instances available for this target.
873 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
875 /// AssemblyParserVariants - The AsmParserVariant instances available for
877 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant];
879 // AssemblyWriters - The AsmWriter instances available for this target.
880 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
883 //===----------------------------------------------------------------------===//
884 // SubtargetFeature - A characteristic of the chip set.
886 class SubtargetFeature<string n, string a, string v, string d,
887 list<SubtargetFeature> i = []> {
888 // Name - Feature name. Used by command line (-mattr=) to determine the
889 // appropriate target chip.
893 // Attribute - Attribute to be set by feature.
895 string Attribute = a;
897 // Value - Value the attribute to be set to by feature.
901 // Desc - Feature description. Used by command line (-mattr=) to display help
906 // Implies - Features that this feature implies are present. If one of those
907 // features isn't set, then this one shouldn't be set either.
909 list<SubtargetFeature> Implies = i;
912 //===----------------------------------------------------------------------===//
913 // Processor chip sets - These values represent each of the chip sets supported
914 // by the scheduler. Each Processor definition requires corresponding
915 // instruction itineraries.
917 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
918 // Name - Chip set name. Used by command line (-mcpu=) to determine the
919 // appropriate target chip.
923 // ProcItin - The scheduling information for the target processor.
925 ProcessorItineraries ProcItin = pi;
927 // Features - list of
928 list<SubtargetFeature> Features = f;
931 //===----------------------------------------------------------------------===//
932 // Pull in the common support for calling conventions.
934 include "llvm/Target/TargetCallingConv.td"
936 //===----------------------------------------------------------------------===//
937 // Pull in the common support for DAG isel generation.
939 include "llvm/Target/TargetSelectionDAG.td"