1 //==-- llvm/MC/MCSubtargetInfo.h - Subtarget Information ---------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subtarget options of a Target machine.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_MC_MCSUBTARGETINFO_H
15 #define LLVM_MC_MCSUBTARGETINFO_H
17 #include "llvm/MC/MCInstrItineraries.h"
18 #include "llvm/MC/SubtargetFeature.h"
25 //===----------------------------------------------------------------------===//
27 /// MCSubtargetInfo - Generic base class for all target subtargets.
29 class MCSubtargetInfo {
30 std::string TargetTriple; // Target triple
31 std::string CPU; // CPU being targeted.
32 ArrayRef<SubtargetFeatureKV> ProcFeatures; // Processor feature list
33 ArrayRef<SubtargetFeatureKV> ProcDesc; // Processor descriptions
35 // Scheduler machine model
36 const SubtargetInfoKV *ProcSchedModels;
37 const MCWriteProcResEntry *WriteProcResTable;
38 const MCWriteLatencyEntry *WriteLatencyTable;
39 const MCReadAdvanceEntry *ReadAdvanceTable;
40 MCSchedModel CPUSchedModel;
42 const InstrStage *Stages; // Instruction itinerary stages
43 const unsigned *OperandCycles; // Itinerary operand cycles
44 const unsigned *ForwardingPaths; // Forwarding paths
45 FeatureBitset FeatureBits; // Feature bits for current CPU + FS
48 void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
49 ArrayRef<SubtargetFeatureKV> PF,
50 ArrayRef<SubtargetFeatureKV> PD,
51 const SubtargetInfoKV *ProcSched,
52 const MCWriteProcResEntry *WPR,
53 const MCWriteLatencyEntry *WL,
54 const MCReadAdvanceEntry *RA,
56 const unsigned *OC, const unsigned *FP);
58 /// getTargetTriple - Return the target triple string.
59 StringRef getTargetTriple() const {
63 /// getCPU - Return the CPU string.
64 StringRef getCPU() const {
68 /// getFeatureBits - Return the feature bits.
70 const FeatureBitset& getFeatureBits() const {
74 /// setFeatureBits - Set the feature bits.
76 void setFeatureBits(const FeatureBitset &FeatureBits_) {
77 FeatureBits = FeatureBits_;
80 /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with
81 /// feature string). Recompute feature bits and scheduling model.
82 void InitMCProcessorInfo(StringRef CPU, StringRef FS);
84 /// InitCPUSchedModel - Recompute scheduling model based on CPU.
85 void InitCPUSchedModel(StringRef CPU);
87 /// ToggleFeature - Toggle a feature and returns the re-computed feature
88 /// bits. This version does not change the implied bits.
89 FeatureBitset ToggleFeature(uint64_t FB);
91 /// ToggleFeature - Toggle a feature and returns the re-computed feature
92 /// bits. This version does not change the implied bits.
93 FeatureBitset ToggleFeature(const FeatureBitset& FB);
95 /// ToggleFeature - Toggle a set of features and returns the re-computed
96 /// feature bits. This version will also change all implied bits.
97 FeatureBitset ToggleFeature(StringRef FS);
99 /// Apply a feature flag and return the re-computed feature bits, including
100 /// all feature bits implied by the flag.
101 FeatureBitset ApplyFeatureFlag(StringRef FS);
103 /// getSchedModelForCPU - Get the machine model of a CPU.
105 MCSchedModel getSchedModelForCPU(StringRef CPU) const;
107 /// getSchedModel - Get the machine model for this subtarget's CPU.
109 const MCSchedModel &getSchedModel() const { return CPUSchedModel; }
111 /// Return an iterator at the first process resource consumed by the given
112 /// scheduling class.
113 const MCWriteProcResEntry *getWriteProcResBegin(
114 const MCSchedClassDesc *SC) const {
115 return &WriteProcResTable[SC->WriteProcResIdx];
117 const MCWriteProcResEntry *getWriteProcResEnd(
118 const MCSchedClassDesc *SC) const {
119 return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries;
122 const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC,
123 unsigned DefIdx) const {
124 assert(DefIdx < SC->NumWriteLatencyEntries &&
125 "MachineModel does not specify a WriteResource for DefIdx");
127 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
130 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
131 unsigned WriteResID) const {
132 // TODO: The number of read advance entries in a class can be significant
133 // (~50). Consider compressing the WriteID into a dense ID of those that are
134 // used by ReadAdvance and representing them as a bitset.
135 for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
136 *E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
137 if (I->UseIdx < UseIdx)
139 if (I->UseIdx > UseIdx)
141 // Find the first WriteResIdx match, which has the highest cycle count.
142 if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
149 /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
151 InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
153 /// Initialize an InstrItineraryData instance.
154 void initInstrItins(InstrItineraryData &InstrItins) const;
156 /// Check whether the CPU string is valid.
157 bool isCPUStringValid(StringRef CPU) {
158 auto Found = std::find_if(ProcDesc.begin(), ProcDesc.end(),
159 [=](const SubtargetFeatureKV &KV) {
160 return CPU == KV.Key;
162 return Found != ProcDesc.end();
166 } // End llvm namespace