1 //=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_MC_MCREGISTERINFO_H
17 #define LLVM_MC_MCREGISTERINFO_H
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/Support/ErrorHandling.h"
25 /// An unsigned integer type large enough to represent all physical registers,
26 /// but not necessarily virtual registers.
27 typedef uint16_t MCPhysReg;
29 /// MCRegisterClass - Base class of TargetRegisterClass.
30 class MCRegisterClass {
32 typedef const MCPhysReg* iterator;
33 typedef const MCPhysReg* const_iterator;
36 const iterator RegsBegin;
37 const uint8_t *const RegSet;
38 const uint16_t RegsSize;
39 const uint16_t RegSetSize;
41 const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes
42 const int8_t CopyCost;
43 const bool Allocatable;
45 /// getID() - Return the register class ID number.
47 unsigned getID() const { return ID; }
49 /// getName() - Return the register class name for debugging.
51 const char *getName() const { return Name; }
53 /// begin/end - Return all of the registers in this class.
55 iterator begin() const { return RegsBegin; }
56 iterator end() const { return RegsBegin + RegsSize; }
58 /// getNumRegs - Return the number of registers in this class.
60 unsigned getNumRegs() const { return RegsSize; }
62 /// getRegister - Return the specified register in the class.
64 unsigned getRegister(unsigned i) const {
65 assert(i < getNumRegs() && "Register number out of range!");
69 /// contains - Return true if the specified register is included in this
70 /// register class. This does not include virtual registers.
71 bool contains(unsigned Reg) const {
72 unsigned InByte = Reg % 8;
73 unsigned Byte = Reg / 8;
74 if (Byte >= RegSetSize)
76 return (RegSet[Byte] & (1 << InByte)) != 0;
79 /// contains - Return true if both registers are in this class.
80 bool contains(unsigned Reg1, unsigned Reg2) const {
81 return contains(Reg1) && contains(Reg2);
84 /// getSize - Return the size of the register in bytes, which is also the size
85 /// of a stack slot allocated to hold a spilled copy of this register.
86 unsigned getSize() const { return RegSize; }
88 /// getAlignment - Return the minimum required alignment for a register of
90 unsigned getAlignment() const { return Alignment; }
92 /// getCopyCost - Return the cost of copying a value between two registers in
93 /// this class. A negative number means the register class is very expensive
94 /// to copy e.g. status flag register classes.
95 int getCopyCost() const { return CopyCost; }
97 /// isAllocatable - Return true if this register class may be used to create
98 /// virtual registers.
99 bool isAllocatable() const { return Allocatable; }
102 /// MCRegisterDesc - This record contains information about a particular
103 /// register. The SubRegs field is a zero terminated array of registers that
104 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers
105 /// of AX. The SuperRegs field is a zero terminated array of registers that are
106 /// super-registers of the specific register, e.g. RAX, EAX, are
107 /// super-registers of AX.
109 struct MCRegisterDesc {
110 uint32_t Name; // Printable name for the reg (for debugging)
111 uint32_t SubRegs; // Sub-register set, described above
112 uint32_t SuperRegs; // Super-register set, described above
114 // Offset into MCRI::SubRegIndices of a list of sub-register indices for each
115 // sub-register in SubRegs.
116 uint32_t SubRegIndices;
118 // RegUnits - Points to the list of register units. The low 4 bits holds the
119 // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
123 /// MCRegisterInfo base class - We assume that the target defines a static
124 /// array of MCRegisterDesc objects that represent all of the machine
125 /// registers that the target has. As such, we simply have to track a pointer
126 /// to this array so that we can turn register number into a register
129 /// Note this class is designed to be a base class of TargetRegisterInfo, which
130 /// is the interface used by codegen. However, specific targets *should never*
131 /// specialize this class. MCRegisterInfo should only contain getters to access
132 /// TableGen generated physical register data. It must not be extended with
135 class MCRegisterInfo {
137 typedef const MCRegisterClass *regclass_iterator;
139 /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be
140 /// performed with a binary search.
141 struct DwarfLLVMRegPair {
145 bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; }
148 const MCRegisterDesc *Desc; // Pointer to the descriptor array
149 unsigned NumRegs; // Number of entries in the array
150 unsigned RAReg; // Return address register
151 unsigned PCReg; // Program counter register
152 const MCRegisterClass *Classes; // Pointer to the regclass array
153 unsigned NumClasses; // Number of entries in the array
154 unsigned NumRegUnits; // Number of regunits.
155 const uint16_t (*RegUnitRoots)[2]; // Pointer to regunit root table.
156 const MCPhysReg *DiffLists; // Pointer to the difflists array
157 const char *RegStrings; // Pointer to the string table.
158 const uint16_t *SubRegIndices; // Pointer to the subreg lookup
160 unsigned NumSubRegIndices; // Number of subreg indices.
161 const uint16_t *RegEncodingTable; // Pointer to array of register
164 unsigned L2DwarfRegsSize;
165 unsigned EHL2DwarfRegsSize;
166 unsigned Dwarf2LRegsSize;
167 unsigned EHDwarf2LRegsSize;
168 const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping
169 const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
170 const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping
171 const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
172 DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping
175 /// DiffListIterator - Base iterator class that can traverse the
176 /// differentially encoded register and regunit lists in DiffLists.
177 /// Don't use this class directly, use one of the specialized sub-classes
179 class DiffListIterator {
181 const MCPhysReg *List;
184 /// Create an invalid iterator. Call init() to point to something useful.
185 DiffListIterator() : Val(0), List(0) {}
187 /// init - Point the iterator to InitVal, decoding subsequent values from
188 /// DiffList. The iterator will initially point to InitVal, sub-classes are
189 /// responsible for skipping the seed value if it is not part of the list.
190 void init(MCPhysReg InitVal, const MCPhysReg *DiffList) {
195 /// advance - Move to the next list position, return the applied
196 /// differential. This function does not detect the end of the list, that
197 /// is the caller's responsibility (by checking for a 0 return value).
199 assert(isValid() && "Cannot move off the end of the list.");
200 MCPhysReg D = *List++;
207 /// isValid - returns true if this iterator is not yet at the end.
208 bool isValid() const { return List; }
210 /// Dereference the iterator to get the value at the current position.
211 unsigned operator*() const { return Val; }
213 /// Pre-increment to move to the next position.
215 // The end of the list is encoded as a 0 differential.
221 // These iterators are allowed to sub-class DiffListIterator and access
222 // internal list pointers.
223 friend class MCSubRegIterator;
224 friend class MCSuperRegIterator;
225 friend class MCRegUnitIterator;
226 friend class MCRegUnitRootIterator;
228 /// \brief Initialize MCRegisterInfo, called by TableGen
229 /// auto-generated routines. *DO NOT USE*.
230 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
232 const MCRegisterClass *C, unsigned NC,
233 const uint16_t (*RURoots)[2],
237 const uint16_t *SubIndices,
239 const uint16_t *RET) {
246 RegStrings = Strings;
248 RegUnitRoots = RURoots;
250 SubRegIndices = SubIndices;
251 NumSubRegIndices = NumIndices;
252 RegEncodingTable = RET;
255 /// \brief Used to initialize LLVM register to Dwarf
256 /// register number mapping. Called by TableGen auto-generated routines.
258 void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size,
262 EHL2DwarfRegsSize = Size;
265 L2DwarfRegsSize = Size;
269 /// \brief Used to initialize Dwarf register to LLVM
270 /// register number mapping. Called by TableGen auto-generated routines.
272 void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size,
276 EHDwarf2LRegsSize = Size;
279 Dwarf2LRegsSize = Size;
283 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
284 /// number mapping. By default the SEH register number is just the same
285 /// as the LLVM register number.
286 /// FIXME: TableGen these numbers. Currently this requires target specific
287 /// initialization code.
288 void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
289 L2SEHRegs[LLVMReg] = SEHReg;
292 /// \brief This method should return the register where the return
293 /// address can be found.
294 unsigned getRARegister() const {
298 /// Return the register which is the program counter.
299 unsigned getProgramCounter() const {
303 const MCRegisterDesc &operator[](unsigned RegNo) const {
304 assert(RegNo < NumRegs &&
305 "Attempting to access record for invalid register number!");
309 /// \brief Provide a get method, equivalent to [], but more useful with a
310 /// pointer to this object.
311 const MCRegisterDesc &get(unsigned RegNo) const {
312 return operator[](RegNo);
315 /// \brief Returns the physical register number of sub-register "Index"
316 /// for physical register RegNo. Return zero if the sub-register does not
318 unsigned getSubReg(unsigned Reg, unsigned Idx) const;
320 /// \brief Return a super-register of the specified register
321 /// Reg so its sub-register of index SubIdx is Reg.
322 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
323 const MCRegisterClass *RC) const;
325 /// \brief For a given register pair, return the sub-register index
326 /// if the second register is a sub-register of the first. Return zero
328 unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
330 /// \brief Return the human-readable symbolic target-specific name for the
331 /// specified physical register.
332 const char *getName(unsigned RegNo) const {
333 return RegStrings + get(RegNo).Name;
336 /// \brief Return the number of registers this target has (useful for
337 /// sizing arrays holding per register information)
338 unsigned getNumRegs() const {
342 /// \brief Return the number of sub-register indices
343 /// understood by the target. Index 0 is reserved for the no-op sub-register,
344 /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers.
345 unsigned getNumSubRegIndices() const {
346 return NumSubRegIndices;
349 /// \brief Return the number of (native) register units in the
350 /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
351 /// can be accessed through MCRegUnitIterator defined below.
352 unsigned getNumRegUnits() const {
356 /// \brief Map a target register to an equivalent dwarf register
357 /// number. Returns -1 if there is no equivalent value. The second
358 /// parameter allows targets to use different numberings for EH info and
360 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
362 /// \brief Map a dwarf register back to a target register.
363 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
365 /// \brief Map a target register to an equivalent SEH register
366 /// number. Returns LLVM register number if there is no equivalent value.
367 int getSEHRegNum(unsigned RegNum) const;
369 regclass_iterator regclass_begin() const { return Classes; }
370 regclass_iterator regclass_end() const { return Classes+NumClasses; }
372 unsigned getNumRegClasses() const {
373 return (unsigned)(regclass_end()-regclass_begin());
376 /// \brief Returns the register class associated with the enumeration
377 /// value. See class MCOperandInfo.
378 const MCRegisterClass& getRegClass(unsigned i) const {
379 assert(i < getNumRegClasses() && "Register Class ID out of range");
383 /// \brief Returns the encoding for RegNo
384 uint16_t getEncodingValue(unsigned RegNo) const {
385 assert(RegNo < NumRegs &&
386 "Attempting to get encoding for invalid register number!");
387 return RegEncodingTable[RegNo];
390 /// \brief Returns true if RegB is a sub-register of RegA.
391 bool isSubRegister(unsigned RegA, unsigned RegB) const {
392 return isSuperRegister(RegB, RegA);
395 /// \brief Returns true if RegB is a super-register of RegA.
396 bool isSuperRegister(unsigned RegA, unsigned RegB) const;
398 /// \brief Returns true if RegB is a sub-register of RegA or if RegB == RegA.
399 bool isSubRegisterEq(unsigned RegA, unsigned RegB) const {
400 return isSuperRegisterEq(RegB, RegA);
403 /// \brief Returns true if RegB is a super-register of RegA or if
405 bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const {
406 return RegA == RegB || isSuperRegister(RegA, RegB);
411 //===----------------------------------------------------------------------===//
412 // Register List Iterators
413 //===----------------------------------------------------------------------===//
415 // MCRegisterInfo provides lists of super-registers, sub-registers, and
416 // aliasing registers. Use these iterator classes to traverse the lists.
418 /// MCSubRegIterator enumerates all sub-registers of Reg.
419 /// If IncludeSelf is set, Reg itself is included in the list.
420 class MCSubRegIterator : public MCRegisterInfo::DiffListIterator {
422 MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
423 bool IncludeSelf = false) {
424 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
425 // Initially, the iterator points to Reg itself.
431 /// MCSuperRegIterator enumerates all super-registers of Reg.
432 /// If IncludeSelf is set, Reg itself is included in the list.
433 class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator {
435 MCSuperRegIterator() {}
436 MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
437 bool IncludeSelf = false) {
438 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
439 // Initially, the iterator points to Reg itself.
445 // Definition for isSuperRegister. Put it down here since it needs the
446 // iterator defined above in addition to the MCRegisterInfo class itself.
447 inline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) const{
448 for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I)
454 //===----------------------------------------------------------------------===//
456 //===----------------------------------------------------------------------===//
458 // Register units are used to compute register aliasing. Every register has at
459 // least one register unit, but it can have more. Two registers overlap if and
460 // only if they have a common register unit.
462 // A target with a complicated sub-register structure will typically have many
463 // fewer register units than actual registers. MCRI::getNumRegUnits() returns
464 // the number of register units in the target.
466 // MCRegUnitIterator enumerates a list of register units for Reg. The list is
467 // in ascending numerical order.
468 class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator {
470 /// MCRegUnitIterator - Create an iterator that traverses the register units
472 MCRegUnitIterator() {}
473 MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) {
474 assert(Reg && "Null register has no regunits");
475 // Decode the RegUnits MCRegisterDesc field.
476 unsigned RU = MCRI->get(Reg).RegUnits;
477 unsigned Scale = RU & 15;
478 unsigned Offset = RU >> 4;
480 // Initialize the iterator to Reg * Scale, and the List pointer to
481 // DiffLists + Offset.
482 init(Reg * Scale, MCRI->DiffLists + Offset);
484 // That may not be a valid unit, we need to advance by one to get the real
485 // unit number. The first differential can be 0 which would normally
486 // terminate the list, but since we know every register has at least one
487 // unit, we can allow a 0 differential here.
492 // Each register unit has one or two root registers. The complete set of
493 // registers containing a register unit is the union of the roots and their
494 // super-registers. All registers aliasing Unit can be visited like this:
496 // for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
497 // for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI)
501 /// MCRegUnitRootIterator enumerates the root registers of a register unit.
502 class MCRegUnitRootIterator {
506 MCRegUnitRootIterator() : Reg0(0), Reg1(0) {}
507 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
508 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
509 Reg0 = MCRI->RegUnitRoots[RegUnit][0];
510 Reg1 = MCRI->RegUnitRoots[RegUnit][1];
513 /// \brief Dereference to get the current root register.
514 unsigned operator*() const {
518 /// \brief Check if the iterator is at the end of the list.
519 bool isValid() const {
523 /// \brief Preincrement to move to the next root register.
525 assert(isValid() && "Cannot move off the end of the list.");
531 /// MCRegAliasIterator enumerates all registers aliasing Reg. If IncludeSelf is
532 /// set, Reg itself is included in the list. This iterator does not guarantee
533 /// any ordering or that entries are unique.
534 class MCRegAliasIterator {
537 const MCRegisterInfo *MCRI;
540 MCRegUnitIterator RI;
541 MCRegUnitRootIterator RRI;
542 MCSuperRegIterator SI;
544 MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI,
546 : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) {
548 // Initialize the iterators.
549 for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) {
550 for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) {
551 for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI) {
552 if (!(!IncludeSelf && Reg == *SI))
559 bool isValid() const {
563 unsigned operator*() const {
564 assert (SI.isValid() && "Cannot dereference an invalid iterator.");
569 // Assuming SI is valid.
571 if (SI.isValid()) return;
575 SI = MCSuperRegIterator(*RRI, MCRI, true);
581 RRI = MCRegUnitRootIterator(*RI, MCRI);
582 SI = MCSuperRegIterator(*RRI, MCRI, true);
587 assert(isValid() && "Cannot move off the end of the list.");
589 while (!IncludeSelf && isValid() && *SI == Reg);
593 } // End llvm namespace