1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "Support/Annotation.h"
20 #include "Support/ilist"
27 class MachineBasicBlock;
31 template <typename T> class ilist_traits;
32 template <typename T> class ilist;
34 typedef short MachineOpCode;
36 //===----------------------------------------------------------------------===//
37 /// MOTy - MachineOperandType - This namespace contains an enum that describes
38 /// how the machine operand is used by the instruction: is it read, defined, or
39 /// both? Note that the MachineInstr/Operator class currently uses bool
40 /// arguments to represent this information instead of an enum. Eventually this
41 /// should change over to use this _easier to read_ representation instead.
45 Use, /// This machine operand is only read by the instruction
46 Def, /// This machine operand is only written by the instruction
47 UseAndDef /// This machine operand is read AND written
51 //===----------------------------------------------------------------------===//
52 // class MachineOperand
55 // Representation of each machine instruction operand.
56 // This class is designed so that you can allocate a vector of operands
57 // first and initialize each one later.
59 // E.g, for this VM instruction:
60 // ptr = alloca type, numElements
61 // we generate 2 machine instructions on the SPARC:
63 // mul Constant, Numelements -> Reg
64 // add %sp, Reg -> Ptr
66 // Each instruction has 3 operands, listed above. Of those:
67 // - Reg, NumElements, and Ptr are of operand type MO_Register.
68 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
70 // For the register operands, the virtual register type is as follows:
72 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
73 // MachineInstr* minstr will point to the instruction that computes reg.
75 // - %sp will be of virtual register type MO_MachineReg.
76 // The field regNum identifies the machine register.
78 // - NumElements will be of virtual register type MO_VirtualReg.
79 // The field Value* value identifies the value.
81 // - Ptr will also be of virtual register type MO_VirtualReg.
82 // Again, the field Value* value identifies the value.
84 //===----------------------------------------------------------------------===//
86 struct MachineOperand {
87 enum MachineOperandType {
88 MO_VirtualRegister, // virtual register for *value
89 MO_MachineRegister, // pre-assigned machine register `regNum'
94 MO_MachineBasicBlock, // MachineBasicBlock reference
95 MO_FrameIndex, // Abstract Stack Frame Index
96 MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool
97 MO_ExternalSymbol, // Name of external global symbol
98 MO_GlobalAddress, // Address of a global value
102 // Bit fields of the flags variable used for different operand properties
104 DEFFLAG = 0x01, // this is a def of the operand
105 USEFLAG = 0x02, // this is a use of the operand
106 HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal)
107 LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal)
108 HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal)
109 LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal)
110 PCRELATIVE = 0x40, // Operand is relative to PC, not a global address
115 Value* value; // BasicBlockVal for a label operand.
116 // ConstantVal for a non-address immediate.
117 // Virtual register for an SSA operand,
118 // including hidden operands required for
119 // the generated machine code.
120 // LLVM global for MO_GlobalAddress.
122 int64_t immedVal; // Constant value for an explicit constant
124 MachineBasicBlock *MBB; // For MO_MachineBasicBlock type
125 std::string *SymbolName; // For MO_ExternalSymbol type
128 char flags; // see bit field definitions above
129 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
130 int regNum; // register number for an explicit register
131 // will be set for a value after reg allocation
133 MachineOperand(int64_t ImmVal = 0, MachineOperandType OpTy = MO_VirtualRegister)
139 MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy)
144 case MOTy::Use: flags = USEFLAG; break;
145 case MOTy::Def: flags = DEFFLAG; break;
146 case MOTy::UseAndDef: flags = DEFFLAG | USEFLAG; break;
147 default: assert(0 && "Invalid value for UseTy!");
151 MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy,
152 bool isPCRelative = false)
153 : value(V), opType(OpTy), regNum(-1) {
155 case MOTy::Use: flags = USEFLAG; break;
156 case MOTy::Def: flags = DEFFLAG; break;
157 case MOTy::UseAndDef: flags = DEFFLAG | USEFLAG; break;
158 default: assert(0 && "Invalid value for UseTy!");
160 if (isPCRelative) flags |= PCRELATIVE;
163 MachineOperand(MachineBasicBlock *mbb)
164 : MBB(mbb), flags(0), opType(MO_MachineBasicBlock), regNum(-1) {}
166 MachineOperand(const std::string &SymName, bool isPCRelative)
167 : SymbolName(new std::string(SymName)), flags(isPCRelative ? PCRELATIVE :0),
168 opType(MO_ExternalSymbol), regNum(-1) {}
171 MachineOperand(const MachineOperand &M) : immedVal(M.immedVal),
175 if (isExternalSymbol())
176 SymbolName = new std::string(M.getSymbolName());
180 if (isExternalSymbol())
184 const MachineOperand &operator=(const MachineOperand &MO) {
185 if (isExternalSymbol()) // if old operand had a symbol name,
186 delete SymbolName; // release old memory
187 immedVal = MO.immedVal;
191 if (isExternalSymbol())
192 SymbolName = new std::string(MO.getSymbolName());
196 /// getType - Returns the MachineOperandType for this operand.
198 MachineOperandType getType() const { return opType; }
200 /// isPCRelative - This returns the value of the PCRELATIVE flag, which
201 /// indicates whether this operand should be emitted as a PC relative value
202 /// instead of a global address. This is used for operands of the forms:
203 /// MachineBasicBlock, GlobalAddress, ExternalSymbol
205 bool isPCRelative() const { return (flags & PCRELATIVE) != 0; }
207 /// isRegister - Return true if this operand is a register operand. The X86
208 /// backend currently can't decide whether to use MO_MR or MO_VR to represent
209 /// them, so we accept both.
211 /// Note: The sparc backend should not use this method.
213 bool isRegister() const {
214 return opType == MO_MachineRegister || opType == MO_VirtualRegister;
217 bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
218 bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; }
219 bool isImmediate() const {
220 return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed;
222 bool isFrameIndex() const { return opType == MO_FrameIndex; }
223 bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; }
224 bool isGlobalAddress() const { return opType == MO_GlobalAddress; }
225 bool isExternalSymbol() const { return opType == MO_ExternalSymbol; }
227 Value* getVRegValue() const {
228 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
232 Value* getVRegValueOrNull() const {
233 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
234 isPCRelativeDisp()) ? value : NULL;
236 int getMachineRegNum() const {
237 assert(opType == MO_MachineRegister);
240 int64_t getImmedValue() const { assert(isImmediate()); return immedVal; }
241 void setImmedValue(int64_t ImmVal) { assert(isImmediate()); immedVal=ImmVal; }
243 MachineBasicBlock *getMachineBasicBlock() const {
244 assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!");
247 int getFrameIndex() const { assert(isFrameIndex()); return immedVal; }
248 unsigned getConstantPoolIndex() const {
249 assert(isConstantPoolIndex());
253 GlobalValue *getGlobal() const {
254 assert(isGlobalAddress());
255 return (GlobalValue*)value;
258 const std::string &getSymbolName() const {
259 assert(isExternalSymbol());
263 bool isUse () const { return flags & USEFLAG; }
264 MachineOperand& setUse () { flags |= USEFLAG; return *this; }
265 bool isDef () const { return flags & DEFFLAG; }
266 MachineOperand& setDef () { flags |= DEFFLAG; return *this; }
267 bool isHiBits32 () const { return flags & HIFLAG32; }
268 bool isLoBits32 () const { return flags & LOFLAG32; }
269 bool isHiBits64 () const { return flags & HIFLAG64; }
270 bool isLoBits64 () const { return flags & LOFLAG64; }
272 // used to check if a machine register has been allocated to this operand
273 bool hasAllocatedReg() const {
274 return (regNum >= 0 &&
275 (opType == MO_VirtualRegister || opType == MO_CCRegister ||
276 opType == MO_MachineRegister));
279 // used to get the reg number if when one is allocated
280 int getAllocatedRegNum() const {
281 assert(hasAllocatedReg());
285 // ********** TODO: get rid of this duplicate code! ***********
286 unsigned getReg() const {
287 return getAllocatedRegNum();
289 void setReg(unsigned Reg) {
290 assert(hasAllocatedReg() && "This operand cannot have a register number!");
294 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
298 // Construction methods needed for fine-grain control.
299 // These must be accessed via coresponding methods in MachineInstr.
300 void markHi32() { flags |= HIFLAG32; }
301 void markLo32() { flags |= LOFLAG32; }
302 void markHi64() { flags |= HIFLAG64; }
303 void markLo64() { flags |= LOFLAG64; }
305 // Replaces the Value with its corresponding physical register after
306 // register allocation is complete
307 void setRegForValue(int reg) {
308 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
309 opType == MO_MachineRegister);
313 friend class MachineInstr;
317 //===----------------------------------------------------------------------===//
318 // class MachineInstr
321 // Representation of each machine instruction.
323 // MachineOpCode must be an enum, defined separately for each target.
324 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
326 // There are 2 kinds of operands:
328 // (1) Explicit operands of the machine instruction in vector operands[]
330 // (2) "Implicit operands" are values implicitly used or defined by the
331 // machine instruction, such as arguments to a CALL, return value of
332 // a CALL (if any), and return value of a RETURN.
333 //===----------------------------------------------------------------------===//
336 short Opcode; // the opcode
337 unsigned char numImplicitRefs; // number of implicit operands
338 std::vector<MachineOperand> operands; // the operands
339 MachineInstr* prev, *next; // links for our intrusive list
340 MachineBasicBlock* parent; // pointer to the owning basic block
341 // OperandComplete - Return true if it's illegal to add a new operand
342 bool OperandsComplete() const;
344 MachineInstr(const MachineInstr &); // DO NOT IMPLEMENT
345 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
348 // Intrusive list support
350 friend class ilist_traits<MachineInstr>;
353 MachineInstr(short Opcode, unsigned numOperands);
355 /// MachineInstr ctor - This constructor only does a _reserve_ of the
356 /// operands, not a resize for them. It is expected that if you use this that
357 /// you call add* methods below to fill up the operands, instead of the Set
358 /// methods. Eventually, the "resizing" ctors will be phased out.
360 MachineInstr(short Opcode, unsigned numOperands, bool XX, bool YY);
362 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
363 /// the MachineInstr is created and added to the end of the specified basic
366 MachineInstr(MachineBasicBlock *MBB, short Opcode, unsigned numOps);
368 const MachineBasicBlock* getParent() const { return parent; }
369 MachineBasicBlock* getParent() { return parent; }
371 /// Accessors for opcode.
373 const int getOpcode() const { return Opcode; }
375 /// Access to explicit operands of the instruction.
377 unsigned getNumOperands() const { return operands.size() - numImplicitRefs; }
379 const MachineOperand& getOperand(unsigned i) const {
380 assert(i < getNumOperands() && "getOperand() out of range!");
383 MachineOperand& getOperand(unsigned i) {
384 assert(i < getNumOperands() && "getOperand() out of range!");
389 // Access to explicit or implicit operands of the instruction
390 // This returns the i'th entry in the operand vector.
391 // That represents the i'th explicit operand or the (i-N)'th implicit operand,
392 // depending on whether i < N or i >= N.
394 const MachineOperand& getExplOrImplOperand(unsigned i) const {
395 assert(i < operands.size() && "getExplOrImplOperand() out of range!");
396 return (i < getNumOperands()? getOperand(i)
397 : getImplicitOp(i - getNumOperands()));
401 // Access to implicit operands of the instruction
403 unsigned getNumImplicitRefs() const{ return numImplicitRefs; }
405 MachineOperand& getImplicitOp(unsigned i) {
406 assert(i < numImplicitRefs && "implicit ref# out of range!");
407 return operands[i + operands.size() - numImplicitRefs];
409 const MachineOperand& getImplicitOp(unsigned i) const {
410 assert(i < numImplicitRefs && "implicit ref# out of range!");
411 return operands[i + operands.size() - numImplicitRefs];
414 Value* getImplicitRef(unsigned i) {
415 return getImplicitOp(i).getVRegValue();
417 const Value* getImplicitRef(unsigned i) const {
418 return getImplicitOp(i).getVRegValue();
421 void addImplicitRef(Value* V, bool isDef = false, bool isDefAndUse = false) {
423 addRegOperand(V, isDef, isDefAndUse);
425 void setImplicitRef(unsigned i, Value* V) {
426 assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!");
427 SetMachineOperandVal(i + getNumOperands(),
428 MachineOperand::MO_VirtualRegister, V);
434 void print(std::ostream &OS, const TargetMachine &TM) const;
436 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
439 // Define iterators to access the Value operands of the Machine Instruction.
440 // Note that these iterators only enumerate the explicit operands.
441 // begin() and end() are defined to produce these iterators...
443 template<class _MI, class _V> class ValOpIterator;
444 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
445 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
448 //===--------------------------------------------------------------------===//
449 // Accessors to add operands when building up machine instructions
452 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the
455 void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) {
456 assert(!OperandsComplete() &&
457 "Trying to add an operand to a machine instr that is already done!");
458 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
459 !isDef ? MOTy::Use : (isDefAndUse ? MOTy::UseAndDef : MOTy::Def)));
462 void addRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use,
463 bool isPCRelative = false) {
464 assert(!OperandsComplete() &&
465 "Trying to add an operand to a machine instr that is already done!");
466 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
470 void addCCRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use) {
471 assert(!OperandsComplete() &&
472 "Trying to add an operand to a machine instr that is already done!");
473 operands.push_back(MachineOperand(V, MachineOperand::MO_CCRegister, UTy,
478 /// addRegOperand - Add a symbolic virtual register reference...
480 void addRegOperand(int reg, bool isDef) {
481 assert(!OperandsComplete() &&
482 "Trying to add an operand to a machine instr that is already done!");
483 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
484 isDef ? MOTy::Def : MOTy::Use));
487 /// addRegOperand - Add a symbolic virtual register reference...
489 void addRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
490 assert(!OperandsComplete() &&
491 "Trying to add an operand to a machine instr that is already done!");
492 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
496 /// addPCDispOperand - Add a PC relative displacement operand to the MI
498 void addPCDispOperand(Value *V) {
499 assert(!OperandsComplete() &&
500 "Trying to add an operand to a machine instr that is already done!");
501 operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp,
505 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
507 void addMachineRegOperand(int reg, bool isDef) {
508 assert(!OperandsComplete() &&
509 "Trying to add an operand to a machine instr that is already done!");
510 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
511 isDef ? MOTy::Def : MOTy::Use));
514 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
516 void addMachineRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
517 assert(!OperandsComplete() &&
518 "Trying to add an operand to a machine instr that is already done!");
519 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
523 /// addZeroExtImmOperand - Add a zero extended constant argument to the
524 /// machine instruction.
526 void addZeroExtImmOperand(int64_t intValue) {
527 assert(!OperandsComplete() &&
528 "Trying to add an operand to a machine instr that is already done!");
529 operands.push_back(MachineOperand(intValue,
530 MachineOperand::MO_UnextendedImmed));
533 /// addSignExtImmOperand - Add a zero extended constant argument to the
534 /// machine instruction.
536 void addSignExtImmOperand(int64_t intValue) {
537 assert(!OperandsComplete() &&
538 "Trying to add an operand to a machine instr that is already done!");
539 operands.push_back(MachineOperand(intValue,
540 MachineOperand::MO_SignExtendedImmed));
543 void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
544 assert(!OperandsComplete() &&
545 "Trying to add an operand to a machine instr that is already done!");
546 operands.push_back(MachineOperand(MBB));
549 /// addFrameIndexOperand - Add an abstract frame index to the instruction
551 void addFrameIndexOperand(unsigned Idx) {
552 assert(!OperandsComplete() &&
553 "Trying to add an operand to a machine instr that is already done!");
554 operands.push_back(MachineOperand(Idx, MachineOperand::MO_FrameIndex));
557 /// addConstantPoolndexOperand - Add a constant pool object index to the
560 void addConstantPoolIndexOperand(unsigned I) {
561 assert(!OperandsComplete() &&
562 "Trying to add an operand to a machine instr that is already done!");
563 operands.push_back(MachineOperand(I, MachineOperand::MO_ConstantPoolIndex));
566 void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative) {
567 assert(!OperandsComplete() &&
568 "Trying to add an operand to a machine instr that is already done!");
569 operands.push_back(MachineOperand((Value*)GV,
570 MachineOperand::MO_GlobalAddress,
571 MOTy::Use, isPCRelative));
574 /// addExternalSymbolOperand - Add an external symbol operand to this instr
576 void addExternalSymbolOperand(const std::string &SymName, bool isPCRelative) {
577 operands.push_back(MachineOperand(SymName, isPCRelative));
580 //===--------------------------------------------------------------------===//
581 // Accessors used to modify instructions in place.
583 // FIXME: Move this stuff to MachineOperand itself!
585 /// replace - Support to rewrite a machine instruction in place: for now,
586 /// simply replace() and then set new operands with Set.*Operand methods
589 void replace(short Opcode, unsigned numOperands);
591 /// setOpcode - Replace the opcode of the current instruction with a new one.
593 void setOpcode(unsigned Op) { Opcode = Op; }
595 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
596 /// fewer operand than it started with.
598 void RemoveOperand(unsigned i) {
599 operands.erase(operands.begin()+i);
602 // Access to set the operands when building the machine instruction
604 void SetMachineOperandVal (unsigned i,
605 MachineOperand::MachineOperandType operandType,
608 void SetMachineOperandConst (unsigned i,
609 MachineOperand::MachineOperandType operandType,
612 void SetMachineOperandReg(unsigned i, int regNum);
615 unsigned substituteValue(const Value* oldVal, Value* newVal,
616 bool defsOnly, bool notDefsAndUses,
617 bool& someArgsWereIgnored);
619 void setOperandHi32(unsigned i) { operands[i].markHi32(); }
620 void setOperandLo32(unsigned i) { operands[i].markLo32(); }
621 void setOperandHi64(unsigned i) { operands[i].markHi64(); }
622 void setOperandLo64(unsigned i) { operands[i].markLo64(); }
625 // SetRegForOperand -
626 // SetRegForImplicitRef -
627 // Mark an explicit or implicit operand with its allocated physical register.
629 void SetRegForOperand(unsigned i, int regNum);
630 void SetRegForImplicitRef(unsigned i, int regNum);
633 // Iterator to enumerate machine operands.
635 template<class MITy, class VTy>
636 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
640 void skipToNextVal() {
641 while (i < MI->getNumOperands() &&
642 !( (MI->getOperand(i).getType() == MachineOperand::MO_VirtualRegister ||
643 MI->getOperand(i).getType() == MachineOperand::MO_CCRegister)
644 && MI->getOperand(i).getVRegValue() != 0))
648 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
653 typedef ValOpIterator<MITy, VTy> _Self;
655 inline VTy operator*() const {
656 return MI->getOperand(i).getVRegValue();
659 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
660 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
662 inline VTy operator->() const { return operator*(); }
664 inline bool isUse() const { return MI->getOperand(i).isUse(); }
665 inline bool isDef() const { return MI->getOperand(i).isDef(); }
667 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
668 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
670 inline bool operator==(const _Self &y) const {
673 inline bool operator!=(const _Self &y) const {
674 return !operator==(y);
677 static _Self begin(MITy MI) {
680 static _Self end(MITy MI) {
681 return _Self(MI, MI->getNumOperands());
685 // define begin() and end()
686 val_op_iterator begin() { return val_op_iterator::begin(this); }
687 val_op_iterator end() { return val_op_iterator::end(this); }
689 const_val_op_iterator begin() const {
690 return const_val_op_iterator::begin(this);
692 const_val_op_iterator end() const {
693 return const_val_op_iterator::end(this);
699 class ilist_traits<MachineInstr>
701 typedef ilist_traits<MachineInstr> self;
703 // this is only set by the MachineBasicBlock owning the ilist
704 friend class MachineBasicBlock;
705 MachineBasicBlock* parent;
708 ilist_traits<MachineInstr>() : parent(0) { }
710 static MachineInstr* getPrev(MachineInstr* N) { return N->prev; }
711 static MachineInstr* getNext(MachineInstr* N) { return N->next; }
713 static const MachineInstr*
714 getPrev(const MachineInstr* N) { return N->prev; }
716 static const MachineInstr*
717 getNext(const MachineInstr* N) { return N->next; }
719 static void setPrev(MachineInstr* N, MachineInstr* prev) { N->prev = prev; }
720 static void setNext(MachineInstr* N, MachineInstr* next) { N->next = next; }
722 static MachineInstr* createNode() { return new MachineInstr(0, 0); }
724 void addNodeToList(MachineInstr* N) {
725 assert(N->parent == 0 && "machine instruction already in a basic block");
729 void removeNodeFromList(MachineInstr* N) {
730 assert(N->parent != 0 && "machine instruction not in a basic block");
734 void transferNodesFromList(iplist<MachineInstr, self>& toList,
735 ilist_iterator<MachineInstr> first,
736 ilist_iterator<MachineInstr> last) {
737 if (parent != toList.parent)
738 for (; first != last; ++first)
739 first->parent = toList.parent;
743 //===----------------------------------------------------------------------===//
746 std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI);
747 std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO);
748 void PrintMachineInstructions(const Function *F);
750 } // End llvm namespace