clk: rockchip: rk3399: keep the pclk_vio is CLK_IGNORE_UNUSED and critical

When we use the MIPI screen, the driver will unprepare and disable
the phy_cfg, it will diable its parent pclk_vio:
dw_mipi_dsi_phy_init
  --> clk_disable_unprepare
    --> clk_disable
      --> clk_core_disable(core->parent)

The pclk_vio supply power for pclk_vio_grf, hence, disable pclk_vio_grf will
cause other drivers failed to operate GRF.

Change-Id: I6d5bd27b9478da09209130f1fd5a62c0d4bb1785
Reported-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

ARM64: dts: rk3399-evb: enable HS400 mode for emmc

We now enable HS400 mode for rk3399-evb for rk folks
to do more test for hs400. If any problem, please remove
mmc-hs400-1_8v from rk3399-evb.dtsi and any reports are
welcomed.

Change-Id: If7d9d291351a075fbb258bd04fce2a2f9cb81be3
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

ARM64: dts: rk3399-evb: add some configure for emmc phy

This patch assign freq-sel, dr-sel, opdelay to meet the
hw requirement of rk3399-evb.

Change-Id: I1ef98645b5414bcffa0b5711bc9eb63f077a5dc3
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

ARM64: dts: rk3399-evb: remove freq limit for sdhci

Change-Id: Ib5916869b79016f6dd4f99389bf723d82355bca3
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

ARM64: dts: rk3399: assign clk parent and rate for SCLK_EMMC

Let's assign clk parent and rate for SCLK_EMMC to meet the
requiremen.

Change-Id: I3730a2124494da51717b1756f488f9df5bcd6423
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

mmc: sdhci-of-arasan: refactor set_clock callback

commit 61b914eb81f8 ("mmc: sdhci-of-arasan: add phy support for
sdhci-of-arasan") introduce phy support for arasan. According to
the vendor's databook, we should make sure the phy is in poweroff
stat before we configure the clk stuff. Otherwise it may cause
some IO sample timing issue from the test. But we don't need this
extra operation while running in non HS200/HS400 mode since phy
doesn't trigger sampling block.

Change-Id: I5506f99e5a3b4d9a4356ad485ceac900c6d754aa
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

phy: rockchip-emmc: fix dllrdy timeout issue

According to the databook, 10.2us is the max time for
dll to be ready to work. However from the test, some chips
need 20us for dll to ready. So this patch add some extra
margin for dllrdy to be ready to meet the reality.

Change-Id: Ie5362b4403309d260ac621b8b20a0f5b579d3153
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

Documentation: bindings: add more configuration for rockchip emmc phy

This patch add some optional configuration for dt. freq-sel can be used
to decide the phy sample clk in order to match the real freq of emmc
controller. dr-sel can be configured to match the requirement of different
drive strength of phy IO. opdelay should be used to adjust the output
delay for clk IO and data IO, which is useful for sloving timing issue.

Change-Id: I0b4da111581c76fbb96b15cd6be653aaa4843c33
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

phy: rockchip-emmc: add some setup configuration

Let's expose the freq-sel, dr-sel, opdalay to dt for user
to decide how to configure their phy.

Change-Id: Ib9ef40b263d3fd669c7bbda666d28c0c55ff6d8e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

ARM64: dts: rockchip: Tiny comment cleanups for kevin-r0

I was having a hard time figuring out where to put new things in
kevin-r0.  Add some comments to explain the sort order.

BUG=None
TEST=Build and boot

Change-Id: I9fb8c200f934542ebed984566bab039d4ec3fd13
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/256509
Commit-Ready: Doug Anderson <dianders@google.com>
Tested-by: Doug Anderson <dianders@google.com>
Reviewed-by: Brian Norris <briannorris@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: dts: rockchip: Remove 'veyron' in kevin/gru compatible

Veyron was an rk3288 board.  Having it in the compatible doesn't make a
ton of sense.  We'll stick 'gru' in the kevin name, though, since that
sorta makes sense.  Not that we ever really fall back to this stuff.

BUG=None
TEST=Build and boot

Change-Id: Ia4b6e02bd9b160c0b20e5459ca441047add2c0bd
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/256508
Commit-Ready: Doug Anderson <dianders@google.com>
Tested-by: Doug Anderson <dianders@google.com>
Reviewed-by: Brian Norris <briannorris@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: dts: rockchip: Fixup revisions for kevin

Turns out that we got mixed up.  Old stuff should just be rev 0.  New
stuff should be rev 1+.  Fix all that.

BUG=None
TEST=Boot rev 0.

Change-Id: I41b38893f1e4224df4e3646cd268179307b3476b
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/256507
Commit-Ready: Doug Anderson <dianders@google.com>
Tested-by: Doug Anderson <dianders@google.com>
Reviewed-by: Brian Norris <briannorris@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

arm64: dts: add kevin r1 and r2

Some pinctrl stuff has moved around and will be identical between gru
and kevin going forward, so kevin r1-specific things will be stored
in the kevin-r1 dts file.

BUG=none
TEST=kernel still boots on kevin-r1

Change-Id: If3e88a57acc40367afca34b5310a59efd70287f6
Signed-off-by: Stephen Barber <smbarber@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/256345
Commit-Ready: Stephen Barber <smbarber@google.com>
Tested-by: Stephen Barber <smbarber@google.com>
Reviewed-by: Doug Anderson <dianders@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

FROMLIST: mfd: cros_ec: Allow building for ARM64

There are platforms using the ChromeOS embeded controller on ARM64 now,
so let's allow using this driver (without having to use COMPILE_TEST).

Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
BUG=none
TEST=make sure we can enable cros_ec for ARM64

Change-Id: I828fec4a2022ea50f10c269ee88ae92c30f48337
Reviewed-on: https://chromium-review.googlesource.com/339540
Commit-Ready: Dan Shi <dshi@google.com>
Tested-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Guenter Roeck <groeck@google.com>
Reviewed-on: https://chrome-internal-review.googlesource.com/256311
Commit-Ready: Brian Norris <briannorris@google.com>
Tested-by: Brian Norris <briannorris@google.com>
Reviewed-by: Doug Anderson <dianders@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

FROMLIST: platform/chrome: cros_ec_dev - Populate compat_ioctl

compat_ioctl has to be populated for 32 bit userspace applications to work
with 64 bit kernels.

BUG=chrome-os-partner:52276
TEST=Build and test with ectool on kevin

Change-Id: I3955d4cf869e4ad4b9f48cdc3b5901cf49dbbe83
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
(am from https://patchwork.kernel.org/patch/8844321/)
Signed-off-by: Guenter Roeck <groeck@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/256310
Commit-Ready: Brian Norris <briannorris@google.com>
Tested-by: Brian Norris <briannorris@google.com>
Reviewed-by: Doug Anderson <dianders@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: dts: gru: fix pwm regulator supplies

The vin-supply binding is valid only for fixed regulators. pwm-supply
should be used for PWM regulators.

Change-Id: I6b65eac6ddc424bb97ba9133b0d67286252b8568
Signed-off-by: Stephen Barber <smbarber@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/255731
Tested-by: Stephen Barber <smbarber@google.com>
Reviewed-by: Doug Anderson <dianders@google.com>

Revert "ARM64: dts: rk3399: gru: Let VOP Big first to select connector device"

We must not to adjust the port order, cause the port id is mapping
to VOP type. Current driver just hardcode that VOP Lit is ID 0, and
VOP Big is ID 1.

        ret = rockchip_drm_encoder_get_mux_id(dp->dev->of_node, encoder);
        if (ret)
                val = dp->data->lcdsel_lit | dp->data->lcdsel_mask;
        else
                val = dp->data->lcdsel_big | dp->data->lcdsel_mask;

Besides eDP could work well with VOP Lit, so we need to revert this
hack. Just revert commit 602f4f79c8f2a833069cd32cb0cc80984e6febb6.

Change-Id: I69badf2860c83c8211ea23b9f490fd4837dcf22e
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

ARM64: dts: rk3399: gpu: add subnode for mali-simple-power-model

Change-Id: I0bd03634631ed30556cc45455582b075692cceba
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

drm/rockchip: analogix_dp: Hack the vop out mode for RK3399 chip

For RK3999 chip, VOP Big/Lit must configure different display out
mode for eDP controller.
  - VOP Lit should output RGB888
  - Vop Big should output RGB10

Change-Id: I85bac6c25a990404682483c62a731681d19eca29
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

drm/rockchip: analogix_dp: distinguish chip type for each chips

Driver could check the chip type to do some special things.

Change-Id: I2a33da466db0aa5133868c200a122df675f4c925
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

drm/rockchip: analogix_dp: rename analogix_dp_data to rockchip_dp_chip_data

Make the data structure name more exactly.

Change-Id: I3d7826ef86d2059cd1557bf4d31b7281377e9fae
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

drm/rockchip: analogix_dp: remove the devtype check in .mode_valid function

The device type would always be ROCKCHIP_DP, so no need to add the
unused devtype check.

Change-Id: I7668a4bdb29700c5397583b9539446f19ae49c3b
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

drm: bridge: analogix_dp: rename RK3288_DP to ROCKCHIP_DP

Change-Id: I05adaad81ea1beabee1fa674bc00f4e044a58913
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

MALI: rockchip: update mali-midgard binding doc

Change-Id: Iffb05ab0032bf0be33652803d4931018e06e0631
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

MALI: rockchip: adjust code about thermal for kernel 4.4

Change-Id: Ic5f3947b032deaaa800ee316636a8cc61259ba5d
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

ARM64: rockchip_defconfig: enable pwm regulator

Change-Id: Id46711f5fd2de5b85e380c146ed77682aaae5376
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

UPSTREAM: ASoC: da7219: Disallow unsupported 32KHz clock setting in set_dai_sysclk()

The PLL function was updated to disallow 32KHz in
commit 501f72e9c520 ("ASoC: da7219: Remove support for 32KHz PLL mode"),
but set_dai_sysclk() was missed and still permits it. This patch resolves
that discrepancy.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from git.kernel.org kernel/git/broonie/sound.git
topic/da7219 commit fb137ba64a6415ddf231495f6d1a82de1cd69ed0)

Change-Id: I1cf8242745f39ac5ae3cb1aa30989bf4ab8f7f93
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ASoC: da7219: Update PLL ranges and dividers to improve locking

The expected MCLK frequency ranges and the associated dividers
are updated to improve PLL locking in a corner scenario, with low
MCLK frequency near an input divider change boundary.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from git.kernel.org kernel/git/broonie/sound.git
topic/da7219 commit 63a450aa4d08ccf4f53e9fa59144e746e2288319)

Change-Id: I7b830ef2ea1e25600365872802924f617b6e0274
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

ARM64: dts: rk3399: evb1-cros: disabled eDP device node

There is a pull up resistor connected to eDP HPD pin on EVB1
hardware, and then eDP controller would always reported that
eDP panel is connected, even if no panel connected.

That would cause driver keep failed on eDP AUX communication,
and lots of annoying error messages would be printed out.

Beside actually the primary panel on EVB1 board is MIPI panel,
few people would have the eDP panel. So let's just disabled
the eDP device on EVB1 board.

Change-Id: Ic2f8b94360821f91e3607c2bfde7d8399fd0080f
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

input: touchscreen: fix kernel crash in fb_notifier_callback function

fb_event would only carry the data number in some special notify action,
other actions wouldn't carry an valid data number, and in this case
kernel would crash, logs like:

[    4.129846] Unable to handle kernel paging request at virtual address 200000000000
......
[    4.164618] Hardware name: Rockchip RK3399 Evaluation Board v1 (Chrome OS) (DT)
[    4.184624] PC is at fb_notifier_callback+0x28/0xac
[    4.189497] LR is at notifier_call_chain+0x74/0xb4
[    4.194279] pc : [<ffffffc0005e1468>] lr : [<ffffffc0000b5ba4>] pstate: 20000045
......
[    5.703780] [<ffffffc0005e1468>] fb_notifier_callback+0x28/0xac
[    5.709690] [<ffffffc0000b5ba4>] notifier_call_chain+0x74/0xb4
[    5.715504] [<ffffffc0000b5e70>] __blocking_notifier_call_chain+0x48/0x64
[    5.722280] [<ffffffc0000b5ea0>] blocking_notifier_call_chain+0x14/0x1c
[    5.728885] [<ffffffc00036fd98>] fb_notifier_call_chain+0x20/0x28
[    5.734969] [<ffffffc0003726c0>] register_framebuffer+0x218/0x250
[    5.741054] [<ffffffc0003b7598>] drm_fb_helper_initial_config+0x2f8/0x374
[    5.747832] [<ffffffc0003e056c>] rockchip_drm_fbdev_init+0xa8/0xe8
[    5.754002] [<ffffffc0003dba24>] rockchip_drm_load+0x1e4/0x25c

Change-Id: I3314315a31bbab43489fca85dabc4c6511fc9dee
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

UPSTREAM: soc: rockchip: power-domain: support qos save and restore

support qos save and restore when power domain on/off.

Change-Id: I5cecf9755467290bc153eeeb75dfd009e7736820
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-armsoc/drivers
 commit 074c6a422d86fff76e05cf31be25e0eb752e1bd4)

UPSTREAM: dt-bindings: modify document of Rockchip power domains

Rockchip Socs contain quality of service (qos) blocks managing priority,
bandwidth, etc of the connection of each domain to the interconnect.
These blocks loose state when their domain gets disabled and therefore
need to be saved when disabling and restored when enabling a power-domain.

These qos blocks also are similar over all currently available Rockchip
SoCs.

Change-Id: I03c80e01ae0fd1a66a67db15f24869047862f13f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-armsoc/drivers
 commit 71daabca344b503f98c59e4bdd53a818cd01f2af)

UPSTREAM: soc: rockchip: power-domain: check the existing of regmap

Check return value of syscon_node_to_regmap for
rockchip_pm_domain_probe. If err value is returned, probe
procedure should abort.

Change-Id: I8b6f2a62d383c5cae5b69e030a8a8e2ad9cc18c1
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-armsoc/drivers
 commit 4506697d9f8537a8d33e9e002f8efceb32d10757)

ARM64: dts: rockchip: rk3366: assign parent for gpu and wifi.

Gpu's 480MHz need to select usbphy_480m as parent.
The jitter will be lower, if sclk_wifidsp is supplied by pll_wifi.

Change-Id: I13e5077d55ab80e5224bac36b469e39d556bd347
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: rk3366: modify the parent's name of usbphy480m

Change-Id: I6a628a96acba4e73405ffc58fbd9a8f6e4544e4f
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

UPSTREAM: clk: Add clk_composite_set_rate_and_parent

When changing the clock-rate, currently a new parent is set first and a
divider adapted thereafter. This may result in the clock-rate overflowing
its target rate for a short time if the new parent has a higher rate than
the old parent.

While this often doesn't produce negative effects, it can affect components
in a voltage-scaling environment, like the GPU on the rk3399 socs, where
the voltage than simply is to low for the temporarily to high clock rate.

For general clock hirarchies this may need more extensive adaptions to
the common clock-framework, but at least for composite clocks having
both parent and rate settings it is easy to create a short-term solution to
make sure the clock-rate does not overflow the target.

Change-Id: Iceb40b24ef13db6947be3d797ea90b3e1055b9df
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from git.kernel.org clk/linux.git clk-next
 commit 9e52cec04fd3b9b686f9256151b47fe61f7c28ef)

UPSTREAM: clk: rockchip: reign in some overly long lines in the rk3399 controller

We allow overlong lines in the array portitions describing the clock
trees to ease readability by having each element always at the same
position. But the rest of the code should honor the 80 char limit.

Fix the newly added rk3399 clock code to respect that.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org kernel/git/mmind/linux-rockchip.git
v4.7-clk/next commit 995d3fdeb2f2d362b1b6bf26656c417452939a1a)

Conflicts:

drivers/clk/rockchip/clk-rk3399.c
[
zx: this patch is based on the old version by Heiko on the upstream:
commit de4939f7fc0a282a4a630e7fcc517ba241340ea0
Author: Xing Zheng <zhengxing@rock-chips.com>
Date:   Fri Mar 25 19:33:48 2016 +0800

    clk: rockchip: rk3399: add some aclk/dclk IDs for vop0/vop1
]

Change-Id: I6aeda93a54ab96ab885f9bf04a5f21b07d1c9a89
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

ARM64: dts: rk3399-fb: include mipi_dsi.h for mipi command mode of timing file

Change-Id: I4426ff9f47abfa7de99b79078370740226871f44
Signed-off-by: Xubilv <xbl@rock-chips.com>

ARM64: dts: rk3368: include mipi_dsi.h for mipi command mode of timing file

Change-Id: Id80b519c7c45678d6163828f4d500f1fc5742343
Signed-off-by: Xubilv <xbl@rock-chips.com>

ARM64: dts: rk3366: include mipi_dsi.h for mipi command mode of timing file

Change-Id: Ib1e43d4df5735c2364138423d9622fd906ff5349
Signed-off-by: Xubilv <xbl@rock-chips.com>

ARM64: configs: rockchip_defconfig: enable DRM RGA support

Change-Id: I8516f9ad6c4c539839135449b36d74649443adf9
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

ARM64: configs: rockchip_cros_defconfig: enable DRM RGA driver support

Change-Id: I4da9799d9e7fc824893b9b19b0e62cc03156ab54
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

ARM64: dts: rk3399: add RGA device node

Change-Id: Ia8bc692fb7395b8dc1bff339aa18282ae91b2024
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

dt-bindings: add document for Rockchip RGA module

RGA is a separate 2D raster graphic acceleration unit.

Change-Id: I510a4799e6c69afe01b2f2adfd6be84e322ff9f2
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

drm/rockchip: add RGA driver support

Rockchip RGA is a separate 2D raster graphic acceleration unit. It
accelerates 2D graphics operations, such as point/line drawing, image
scaling, rotation, BitBLT, alpha blending and image blur/sharpness.

Change-Id: I9be8d683ea04802affb973b8b1ada646afe411d7
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

drm/rockchip: add a common subdrv interfaces

Introduce a common subdrv register/unregister interfaces, help
sub-driver to hook the drm open/close event.

Change-Id: I42a563504dd8d8e26f34946067e6e60f1ee88379
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

ARM64: dts: rk3399-fb: enable vop iommu

Change-Id: I42fd20b89205d53f539ab37ce65347d3c7b4ce9e
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: vop: 3399: update for AFBDC

1.gpu afbc default in yuv color;
2.mb width and hight is equal to xvir and yvir.

Change-Id: I905d90c8a75c0b5136ff883fbcf7128ca954e425
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: fb: add vopid for screen switch uevent

Change-Id: Ib51af94397758a2118b6a41e1c736ac454e12b85
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

regulator: mp8865: update mp8865 driver

set slew rate 1.6mV/uS, set switch_frequency 1.1MHz,
support enable_time 100us and add regmap cache.

Change-Id: I8fb2147b5a574ab96f5e3601cb5ac24412676045
Signed-off-by: Zain Wang <wzz@rock-chips.com>

ARM64: dts: rk3399: add dts files for evb rev2

Change-Id: I40abefbae2377f4f86a54b5b752b831acd592d10
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

ARM64: dts: rk3399: rename dts files

Rename the rk3399 dts files:
    rk3399-monkey.dts -> rk3399-evb1-android.dts
    rk3399-chrome.dts -> rk3399-evb1-cros.dts
    rk3399-tb.dtsi -> rk3399-evb.dtsi

Change-Id: Ie1f61d63b8fefc263a64d713d70947ceee8472c5
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

clk: rockchip: rk3399: Export isp clock IDs

Change-Id: I6f8a2192d6f69b23ba4fa3ad6e973aba9120399a
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: rk3399: Add and export SCLK_RGA_CORE clock id

Change-Id: Ia64289f565e7b4570c6b55810bda5d4711a7381a
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

usb: gadget: composite: don't queue OS desc request if req length is invalid

In OS descriptors handling, if ctrl->bRequestType is USB_RECIP_DEVICE
and w_index != 0x4 or (w_value >> 8) is true, it will not reset
req->length, but use the default value(-EOPNOTSUPP), and queue an
OS desc request with an invalid req->length. It always happens
on the platforms which use os_desc(for example: rk3366,rk3399),
and cause kernel panic as follows(use dwc3 driver):

Unable to handle kernel paging request at virtual address ffffffc0f7e00000
Internal error: Oops: 96000146 [#1] PREEMPT SMP
PC is at __dma_clean_range+0x18/0x30
LR is at __swiotlb_map_page+0x50/0x64
Call trace:
 [<ffffffc0000930f8>] __dma_clean_range+0x18/0x30
 [<ffffffc00062214c>] usb_gadget_map_request+0x134/0x1b0
 [<ffffffc0005c289c>] __dwc3_ep0_do_control_data+0x110/0x14c
 [<ffffffc0005c2d38>] __dwc3_gadget_ep0_queue+0x198/0x1b8
 [<ffffffc0005c2e18>] dwc3_gadget_ep0_queue+0xc0/0xe8
 [<ffffffc00061cfec>] composite_ep0_queue.constprop.14+0x34/0x98
 [<ffffffc00061dfb0>] composite_setup+0xf60/0x100c
 [<ffffffc0006204dc>] android_setup+0xd8/0x138
 [<ffffffc0005c29a4>] dwc3_ep0_delegate_req+0x34/0x50
 [<ffffffc0005c3534>] dwc3_ep0_interrupt+0x5dc/0xb58
 [<ffffffc0005c0c3c>] dwc3_thread_interrupt+0x15c/0xa24

With this patch, the gadget driver will not queue a request and
return immediately if req->length is invalid. And the usb controller
driver can handle the unsupport request correctly.

Change-Id: I60270d7c12fa190a99cd1079880a2f7167e7af27
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

video: rockchip: mipi: rk3399: add power domain control

Change-Id: I61c2ad075417a716b1ba7c73baf4fd5889b402e9
Signed-off-by: Xubilv <xbl@rock-chips.com>

video: rockchip: vop: 3399: fix afbdc abnormal

The vop mask write need use u64 value.

Change-Id: I020fdf4e7115b2763dd732be6542589f61190f4a
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

FROMLIST: thermal: rockchip: disable thermal->clk in err case

Disable thermal->clk when enabling pclk fails in
resume routine.

Change-Id: I7d8780be04891bf4cddf1ba970eae2a2f14ec7ac
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
(am from https://patchwork.kernel.org/patch/8867151/)

usb: dwc3: fix compile failure if config host only mode

This patch fixes following compile error in dwc3 if select
CONFIG_USB_DWC3_HOST.

drivers/usb/dwc3/core.c:874: undefined reference to `dwc3_gadget_restart'
drivers/usb/dwc3/core.c:880: undefined reference to `dwc3_gadget_restart'

which was caused by commit
commit 9607f47dfec23c5773d74e45ed561859eabce2b7
usb: dwc3: add functions to set force mode

Change-Id: Id0abaf89fba006609dbf2e7a771149453465b371
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

video: rockchip: vop: 3399: add power domain control

Change-Id: Ie10029456b2a62a30c5571131c142e0468f86d48
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

ARM64: dts: rk3399: update cpu and gpu opp tables

Change-Id: Ic27e5e0f9e74db8eb3fb2048127e7e0d6ca1bd92
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>

ARM64: dts: rockchip: add thermal zone node for rk3399 SoCs

This adds thermal zone node to rk3399 dtsi, rk3399 thermal data is
including the cpu and gpu sensor zone node.
At the moment, remove the rk3368 thermal data from rk399 dtsi.

The thermal zone node is the node containing all the required info
for describing a thermal zone, including its cooling device bindings. The
thermal zone node must contain, apart from its own properties, one sub-node
containing trip nodes and one sub-node containing all the zone cooling maps

The following is the parameter is introduced:

* polling-delay:
The maximum number of milliseconds to wait between polls

* polling-delay-passive:
The maximum number of milliseconds to wait between polls when performing
passive cooling.

* trips:
A sub-node which is a container of only trip point nodes required to describe
the thermal zone.

* cooling-maps:
A sub-node which is a container of only cooling device map nodes, used to
describe the relation between trips and cooling devices.

* cooling-device:
A phandle of a cooling device with its specifier, referring to which cooling
device is used in this cooling specifier binding. In the cooling specifier,
the first cell is the minimum cooling state and the second cell is the maximum
cooling state used in this map.

Change-Id: I76c5829fdc120cd5da078e2937abeee720ee379c
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

thermal: rockchip: add the set_trips function

Whenever the current temperature is updated, the trip points immediately
below and above the current temperature are found. A sensor driver
callback `set_trips' is then called with the temperatures.
Lastly, The sensor will trigger the hardware high temperature interrupts
to increase the sampleing rate and throttle frequency to limit the temperature
rising When performing passive cooling.

Change-Id: I43d37a8431240cb7b62da7bff83464aba3c8983e
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

CHROMIUM: thermal: of: Add support for hardware-tracked trip points

This adds support for hardware-tracked trip points to the device tree
thermal sensor framework.

The framework supports an arbitrary number of trip points. Whenever
the current temperature is updated, the trip points immediately
below and above the current temperature are found. A sensor driver
callback `set_trips' is then called with the temperatures.
If there is no trip point above or below the current temperature,
the passed trip temperature will be LONG_MAX or LONG_MIN respectively.
In this callback, the driver should program the hardware such that
it is notified when either of these trip points are triggered.
When a trip point is triggered, the driver should call
`thermal_zone_device_update' for the respective thermal zone. This
will cause the trip points to be updated again.

If the `set_trips' callback is not implemented (is NULL), the framework
behaves as before.

CQ-DEPEND=CL:*210768
BUG=chrome-os-partner:30834
TEST=None

Change-Id: I33226d2b80f3e71a0c3ca3fbc5718db4e461268f
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
Signed-off-by: Wei Ni <wni@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/212425
Reviewed-by: Olof Johansson <olofj@chromium.org>
Commit-Queue: Olof Johansson <olofj@chromium.org>
Tested-by: Olof Johansson <olofj@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/210454
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Dylan Reid <dgreid@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/267514
Tested-by: David Riley <davidriley@chromium.org>
Reviewed-by: David Riley <davidriley@chromium.org>
Commit-Queue: David Riley <davidriley@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
(cherry-picked from https://chromium.googlesource.com/chromiumos/
 third_party/kernel/+/v3.18 commit 397befabb2a52fc16586509a970f8c98268b8040)

ARM64: config: add the thermal needed configure for rockchip

We need the cpu throttle and IPA function for rockchip.
Also enable the writable trips function.

Let's enable the needed config for thermal.

Change-Id: Ibd43aa4ef3cc5e0a325e376d753cffc8bcdb8c02
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

clk: rockchip: rk3399: add 216M and 96M for armclkb and armclkl

support 216M/96M for armclkb and armclkl

Change-Id: I26bf94ab0b27863a438b52be29e1a3aa208fa6ff
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

ARM64: dts: rk3399: don't let VOP LIT first to select eDP device

The endpoint order would decide the priority of connector devices,
the higher the priority ranking.

For now eDP can't light up with VOP Lit, so we need to cut down
the priority that eDP in VOP Lit, and raise up the priority that
MIPI in VOP Lit.

Change-Id: Ide4e321f03cf7ad5080c6db7f9230962963a3eb8
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

ARM64: dts: rk3399: gru: Let VOP Big first to select connector device

This is a hack way to let VOP Big to select eDP device when VOP
Big and Lit all enabled.

Change-Id: Ia2bc91ff903bbc7d00deed57aab315328ce54378
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

clk: rockchip: rk3399: fix clk_cifout setting clk error

Fix a typo making the clk_cifout access a
wrong clk tree to handle its mux and div.

Change-Id: Ief20e684eadd10b75cf36120df16f13c7581d303
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

ARM64: dts: rk3399: gru: add backlight and eDP panel device nodes

Panel brightness is controller by EC, the AP just enable/disable the
backlight power through GPIO1_C1.

Change-Id: I46e1f3b5098159cb07f86ba203ef8cfa102dd385
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: dts: rk3399: chrome: enable eDP support

The RK3399 EVB board is using the LG LP097QX1-SPA1
9.7" 2048x1536 eDP panel.

Change-Id: I837b0a569605591756918b12f56dbaa0b1f3f8d4
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

HACK: ARM64: dts: rockchip: Hack out PWM regulators on gru

Until we get PWM regulator solid, let's hack it out and just keep
whatever the firmware set for us.

Note that when the kernel boots it appears that it does some reparenting
of clocks and the PWM frequency actually changes.  ...but the voltage
seems OK ish.

Change-Id: I3be6ea4460f685e4a75a0f7f31f767f09b908442
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/254650
Reviewed-by: Stephen Barber <smbarber@google.com>
Tested-by: Doug Anderson <dianders@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
(Fixes the typo)

ARM64: dts: rockchip: rk808: set the dvs2 gpio pull down

the hw default of the dvs2 is pull up which is not correct.
set the dvs2 gpio pull down.

Change-Id: I0d296cecc422456cb72630d5ce64a5c7e5dad283
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

HACK: clk: rockchip: rk3399: Mark the PWM clock as critical

Until we get all the magic PWM regulator stuff solved with Boris's
wonderful upstream patches, let's just hack the PWM clock to be critical
so it never turns off.  Nuff said.

Change-Id: I99660b0b188413eb08030a3ae87c045c338b30db
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/254649
Reviewed-by: Stephen Barber <smbarber@google.com>
Tested-by: Doug Anderson <dianders@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
(Fixes the pclk_rkpwm_pmu into pmucru_critical_clock)

ARM64: rockchip_cros_defconfig: cleanup for defconfig

We should make sure the config generate from the savedefconfig.
Okay, anyway cleanup the config with run 'make ARCH=arm64 savedefconfig'.

Change-Id: Ia094322870d378183760e32b7177971342e48439
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: dts: rk3399: gru: enable GPU device node

Change-Id: I2edad7d66cf655cb96ac6c933fdece9734eda469
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

ARM64: rockchip_cros_defconfig: enable GPIO BACKLIGHT

The eDP panel of Kevin board only have a AP GPIO to control
the backlight power, so we need to enable the GPIO backlight
type for it.

Change-Id: I939e1c658b56ee5d889af820985f9ffd46f50485
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

dt-bindings: add Samsung LSN122DL01-C01 panel binding

The Samsung LSN122DL01-C01 is an 12.2" 2560x1600 (WQXGA) TFT-LCD
panel connected using eDP interfaces.

Change-Id: Ib5164763d18c5cffcc83b38715f559a4a0c02638
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

drm/panel: simple: Add support for Samsung LSN122DL01-C01 2560x1600 panel

The Samsung LSN122DL01-C01 is an 12.2" 2560x1600 (WQXGA) TFT-LCD panel
connected using eDP interfaces.

Change-Id: I3c2208fc45b53b0fab328fcb9ba204f610a9f9f6
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

ARM: dts: rk3366-tb: adjust tx & rx delayline for 1000BT ethernet

Change-Id: I4d5f7150178d8f6f7e78f9109e49c73956aefaee
Signed-off-by: roger <roger.chen@rock-chips.com>

ARM64: dts: rockchip: fixes the hw-tshut-polarity for rk3399

AFAIK, the hardware designed that TSHUT should be set the active high.

Since rk3399 evb designed the over-temperature protection pin is
connected to PMIC that active high vaild.
Also, as gru/kevin designed the over-temperature protection pin is
connected to EC control that active high to prevent leakage.

Change-Id: Ib7b15d115d2ea4e474918fc416dde273b040e740
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

drm: rockchip: analogix_dp: update the comments about why need to hardcode VOP output mode

The hardware IC designed that VOP must output the RGB10 video format to
eDP contoller, and if eDP panel only support RGB8, then eDP contoller
should cut down the video data, not via VOP contoller, that's why we need
to hardcode the VOP output mode to RGA10 here.

Change-Id: I733eae8a5dda51c0288d8627ceffb39a2f804e62
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

drm: rockchip: analogix_dp: correct the connector display color format and bpc

Rockchip VOP couldn't output YUV video format for eDP controller, so
when driver detect connector support YUV video format, we could hack
it down to RGB888.

Change-Id: Ia876bb49e772f85bef201af2b62dd558d6b99257
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

drm/bridge: analogix_dp: introduce connector mode_valid callback to plat driver

It's helpful to expand the mode_valid callback to platform driver,
so they could valid the display mode or informations.

Change-Id: Icfd7593bd10c93fc9045acf04a8d0ed6336ffb85
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

drm/rockchip: analogix_dp: make panel detect to an optional action

Some boards don't need to declare a panel device node, like the
display interface is DP monitors, so it's necessary to make the
panel detect to an optional action.

Change-Id: I0146e9f9fb2e35b5878ab114e8aa1df35ba4843d
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

Revert "drm/bridge: analogix_dp: hardcode input video format to RGB10 for Rockchip platform"

On RK3399 EVB board, the LG panel only support RGB888. so with previous
changes, VOP would send the RGB10 video format to panel, and then panel
just display abnormally.

This reverts commit 144e62cef352d9670f09de3ac1da53ca6182835c.

Change-Id: I09a5ab0aa8758e87e8b7f2fc20fbbaa113fe1d33
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

ARM64: dts: rockchip: Remove default sample phase from gru

It looks like the addition of default-sample-phase to the GRU dts is
what was causing my periodic boot failures.  After removing it I found
that I could get 25+ reboots with no failures.  Calling it good.

BUG=None
TEST=Reboot many times; see successful boot each time.

Change-Id: Id200957da9d9a2eb81ce63dcb57c4f0f5e94e72d
Signed-off-by: Douglas Anderson <dianders@chromium.org>

UPSTREAM: drm: prime: Honour O_RDWR during prime-handle-to-fd

Currently DRM_IOCTL_PRIME_HANDLE_TO_FD rejects all flags except
(DRM|O)_CLOEXEC making it difficult (maybe impossible) for userspace
to mmap() the resulting dma-buf even when this is supported by the
DRM driver.

It is trivial to relax the restriction and permit read/write access.
This is safe because the flags are seldom touched by drm; mostly they
are passed verbatim to dma_buf calls.

v3 (Tiago): removed unused flags variable from drm_prime_handle_to_fd_ioctl.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Signed-off-by: Tiago Vignatti <tiago.vignatti@intel.com>
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1450820214-12509-2-git-send-email-tiago.vignatti@intel.com
(cherry picked from commit bfe981a0952880df43d08a050bf3ae44aaebd795)
Signed-off-by: Brian Norris <briannorris@chromium.org>
Change-Id: Ieb3c547b1a08bd9c90fe72e0a1df1757d100aa8e
Reviewed-on: https://chrome-internal-review.googlesource.com/255266
Tested-by: Brian Norris <briannorris@google.com>
Reviewed-by: Doug Anderson <dianders@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: dts: rk3399-tb: adjust tx & rx delayline for 1000BT ethernet

Change-Id: I36dfc4d1289e388c7a955f3ba0e7f974b39d28fd
Signed-off-by: roger <roger.chen@rock-chips.com>

thermal: rockchip: add the notes for better reading

To update the notes for keeping in mind that quickly in case
someone re-read this driver in the future.

Change-Id: Ic752ed1d6a818f21560befd981383e8b532dff36
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

thermal: rockchip: add the interleave value setting

The interleave is between power down and start of conversion,
This patch adds to workaround ic time sync issue for control.

Change-Id: Ib9f28fd92bcecf8ddaa8a69d47ced87fef04e7c6
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

thermal: rockchip: Support RK3366 SoCs in the thermal driver

The RK3366 SoCs have two Temperature Sensors, channel 0 is for CPU
channel 1 is for GPU.

Change-Id: I71324c65e82804f52d464b986e1d86127f8dc040
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

ARM64: rockchip_cros_defconfig: enable /proc/config.gz

This helps to be absolutely sure of what CONFIG_* switches are enabled
for your build.

Change-Id: Ic1043d78b01502af9f5a2d4776672c66fc152f5c
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/254936
Commit-Queue: Brian Norris <briannorris@google.com>
Tested-by: Brian Norris <briannorris@google.com>
Reviewed-by: Stephen Barber <smbarber@google.com>

ARM64: dts: rockchip: Force pp3300_disp regulator to stay on

Normally, the display regulator would be kept powered on by the
display/backlight driver, but we don't yet have a DT representation or
driver for this, as the PWM is controlled by the EC. Just force the
regulator on for now.

This wasn't needed on some boards yet, since they were forcing this
regulator "on." But for those where we might be controlling it, we need
this. (And it's harmless otherwise.)

This is necessary but not sufficient for getting UI up on my board.

Change-Id: I30650c178dd42d76542f8f2491e22d9bf548363e
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/254935
Commit-Queue: Brian Norris <briannorris@google.com>
Tested-by: Brian Norris <briannorris@google.com>
Reviewed-by: Stephen Barber <smbarber@google.com>

ARM64: rockchip_cros_defcofnig: enable DA7219 manchine driver and codec

Change-Id: Iaf0f1f63b6f1b8f0e3f391b1d900b201d59b9660
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

ARM64: dts: gru: Add support machine driver for DA7219

Now, we can playback and capture via DA7219 machine driver call the
da7219_aad_jack_det (simple-card can not do this).

Change-Id: I8b1be189031f875b1c5328e9357115761a5f4da3
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

ASoC: rockchip: Add support machine driver for DA7219

The DA7219 only support headphone playback, we may not call the
da7219_aad_jack_det when we use the simple-card.

Therefore, the machine driver may be need to submit upstream.

Change-Id: Iecf53fa62fcaf43175bbbcd2b7c8b0d5c67655ac
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: rk3399: Add CLK_SET_RATE_PARENT for main VOP0

We recommend, VOP0 is the main screen, VOP1 is a sub screen,
only VOP0 is able to re-set parent (VPLL) rate.

Change-Id: If40f95ce18e73477df8f7f031013333a603d5eb2
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: rk3399: Modify dummy clock for VOP dclks

Because frac div need to more than 20 multiple between the numerator
and denominator, but we need to be fit many HDMI/DP freqs and may
bring serious jitter when the dclk_vopx below the dclk_vopx_frac.

Therefore, we can select dclk_vopx below the dclk_vopx_div directly.

Change-Id: If3d9051211f0b160a507f0942667796f043f4ec2
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ASoC: da7219: Correct BCLK inversion for DSP DAI format mode

By default the device latches data on the falling edge of the
BCLK in DSP mode, whereas the expectation for normal BCLK is to
latch on the rising edge. This updates the driver to invert the
BCLK configuration for DSP mode, to align with expected behaviour.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 4acfa36be618eb8ac3aa39f473e7550710216435)

Change-Id: I646f6ec9fb377ce95d90d57c80dc05f13b6696f2
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>