u32 cru_clksel0_con;
u32 clkgt_regs[CRU_CLKGATES_CON_CNT];
int i;
+ u32 grf_uoc1_con;
sram_printch('5');
ddr_suspend();
board_pmu_suspend();
sram_printch('7');
-
+ grf_uoc1_con = grf_readl(GRF_UOC1_CON4);
+ grf_writel(0x30000000,GRF_UOC1_CON4);
for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
clkgt_regs[i] = cru_readl(CRU_CLKGATES_CON(i));
}
cru_writel(clkgt_regs[i] | 0xffff0000, CRU_CLKGATES_CON(i));
}
+ grf_writel(0x30000000|grf_uoc1_con,GRF_UOC1_CON4);
sram_printch('7');
board_pmu_resume();
rk30_pwm_logic_resume_voltage();