rk fb:add more screen property
authoryxj <yxj@rock-chips.com>
Fri, 21 Feb 2014 10:36:47 +0000 (18:36 +0800)
committeryxj <yxj@rock-chips.com>
Tue, 25 Feb 2014 01:26:46 +0000 (09:26 +0800)
arch/arm/boot/dts/lcd-b101ew05.dtsi
drivers/video/of_display_timing.c
drivers/video/rockchip/rk_fb.c
include/dt-bindings/rkfb/rk_fb.h
include/linux/rk_fb.h
include/linux/rk_screen.h
include/video/display_timing.h

index e0c2db4f92c99ff1867bb1038b183b67e84bc5c9..b3187f4661d687340b2182279db79e04b861953f 100644 (file)
@@ -8,19 +8,19 @@
                         rockchip,debug = <0>;
                         lcd_en:lcd_en {
                                 rockchip,power_type = <GPIO>;
-                                gpios = <&gpio0 GPIO_B0 1>;
+                                gpios = <&gpio0 GPIO_B0 GPIO_ACTIVE_HIGH>;
                                 rockchip,delay = <10>;
                         };
 
                      /*   bl_en:bl_en {
                                 rockchip,power_type = <GPIO>;
-                                gpios = <&gpio0 GPIO_A2 1>;
+                                gpios = <&gpio0 GPIO_A2 GPIO_ACTIVE_HIGH>;
                                 rockchip,delay = <10>;
                         };
 
                         bl_ctr:bl_ctr {
                                 rockchip,power_type = <GPIO>;
-                                gpios = <&gpio3 GPIO_D6 1>;
+                                gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>;
                                 rockchip,delay = <10>;
                         };
 
                disp_timings: display-timings {
                         native-mode = <&timing0>;
                         timing0: timing0 {
+                               screen_type = <SCREEN_LVDS>;
+                               lvds_format = <LVDS_8BIT_2>;
+                               out_face    = <OUT_D888_P666>;
                                clock-frequency = <71000000>;
                                hactive = <1280>;
-                                vactive = <800>;
-                                hback-porch = <100>;
-                                hfront-porch = <18>;
-                                vback-porch = <8>;
-                                vfront-porch = <6>;
-                                hsync-len = <10>;
-                                vsync-len = <2>;
-                                hsync-active = <0>;
-                                vsync-active = <0>;
-                                de-active = <1>;
-                                pixelclk-active = <0>;
+                               vactive = <800>;
+                               hback-porch = <100>;
+                               hfront-porch = <18>;
+                               vback-porch = <8>;
+                               vfront-porch = <6>;
+                               hsync-len = <10>;
+                               vsync-len = <2>;
+                               hsync-active = <0>;
+                               vsync-active = <0>;
+                               de-active = <0>;
+                               pixelclk-active = <0>;
+                               swap-rb = <0>;
+                               swap-rg = <0>;
+                               swap-gb = <0>;
                        };
                };
 };
index 56009bc02b02475b525966ee9b8239d4a779b56d..26443ef3d7dbcc9d055773b67dacacfb9adfa816 100644 (file)
@@ -98,6 +98,21 @@ static struct display_timing *of_get_display_timing(struct device_node *np)
        if (of_property_read_bool(np, "doublescan"))
                dt->flags |= DISPLAY_FLAGS_DOUBLESCAN;
 
+#if defined(CONFIG_FB_ROCKCHIP)
+       if (!of_property_read_u32(np, "swap-rg", &val))
+               dt->flags |= val ? DISPLAY_FLAGS_SWAP_RG : 0;
+       if (!of_property_read_u32(np, "swap-gb", &val))
+               dt->flags |= val ? DISPLAY_FLAGS_SWAP_GB : 0;
+       if (!of_property_read_u32(np, "swap-rb", &val))
+               dt->flags |= val ? DISPLAY_FLAGS_SWAP_RB : 0;
+       if (!of_property_read_u32(np, "screen-type", &val))
+               dt->screen_type = val;
+       if (!of_property_read_u32(np, "lvds-format", &val))
+               dt->lvds_format = val;
+       if (!of_property_read_u32(np, "out-face", &val))
+               dt->face = val;
+#endif
+
        if (ret) {
                pr_err("%s: error reading timing properties\n",
                        of_node_full_name(np));
index 0032769dbeb5f63c6db640d8bc3bba6a9bbdcff3..e1844e7b2b9d78315787d9762060268ba9a9ed3a 100755 (executable)
@@ -92,7 +92,7 @@ int rk_disp_pwr_ctr_parse_dt(struct rk_lcdc_driver *dev_drv)
                                        dev_err(dev_drv->dev, "%s ivalid gpio\n", child->name);
                                        return -EINVAL;
                                }
-                               pwr_ctr->pwr_ctr.atv_val = flags & OF_GPIO_ACTIVE_LOW;
+                               pwr_ctr->pwr_ctr.atv_val = !(flags & OF_GPIO_ACTIVE_LOW);
                                ret = gpio_request(pwr_ctr->pwr_ctr.gpio,child->name);
                                if (ret) {
                                        dev_err(dev_drv->dev, "request %s gpio fail:%d\n",
@@ -168,7 +168,41 @@ int rk_disp_pwr_disable(struct rk_lcdc_driver *dev_drv)
        return 0;
 }
 
-
+int rk_fb_video_mode_from_timing(const struct display_timing *dt, 
+                               struct rk_screen *screen)
+{
+       screen->mode.pixclock = dt->pixelclock.typ;
+       screen->mode.left_margin = dt->hback_porch.typ;
+       screen->mode.right_margin = dt->hfront_porch.typ;
+       screen->mode.xres = dt->hactive.typ;
+       screen->mode.hsync_len = dt->hsync_len.typ;
+       screen->mode.upper_margin = dt->vback_porch.typ;
+       screen->mode.lower_margin = dt->vfront_porch.typ;
+       screen->mode.yres = dt->vactive.typ;
+       screen->mode.vsync_len = dt->vsync_len.typ;
+       screen->type = dt->screen_type;
+       screen->lvds_format = dt->lvds_format;
+       screen->face = dt->face;
+       if (dt->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
+               screen->pin_dclk = 1;
+       else
+               screen->pin_dclk = 0;
+       if(dt->flags & DISPLAY_FLAGS_HSYNC_HIGH)
+               screen->pin_hsync = 1;
+       else
+               screen->pin_hsync = 0;
+       if(dt->flags & DISPLAY_FLAGS_VSYNC_HIGH)
+               screen->pin_vsync = 1;
+       else
+               screen->pin_vsync = 0;
+       if(dt->flags & DISPLAY_FLAGS_DE_HIGH)
+               screen->pin_den = 1;
+       else
+               screen->pin_den = 0;
+       
+       return 0;
+       
+}
 int rk_disp_prase_timing_dt(struct rk_lcdc_driver *dev_drv)
 {
        struct display_timings *disp_timing;
@@ -180,16 +214,7 @@ int rk_disp_prase_timing_dt(struct rk_lcdc_driver *dev_drv)
                return -EINVAL;
        }
        dt = display_timings_get(disp_timing, 0);
-
-       screen->mode.pixclock = dt->pixelclock.typ;
-       screen->mode.left_margin = dt->hback_porch.typ;
-       screen->mode.right_margin = dt->hfront_porch.typ;
-       screen->mode.xres = dt->hactive.typ;
-       screen->mode.hsync_len = dt->hsync_len.typ;
-       screen->mode.upper_margin = dt->vback_porch.typ;
-       screen->mode.lower_margin = dt->vfront_porch.typ;
-       screen->mode.yres = dt->vactive.typ;
-       screen->mode.vsync_len = dt->vsync_len.typ;
+       rk_fb_video_mode_from_timing(dt, screen);
        printk(KERN_DEBUG "dclk:%d\n"
                         "hactive:%d\n"
                         "hback_porch:%d\n"
@@ -358,10 +383,12 @@ static struct rk_lcdc_driver  *rk_get_extend_lcdc_drv(void)
        return dev_drv;
 }
 
-struct rk_screen *rk_fb_get_prmry_screen(void)
+int rk_fb_get_prmry_screen(struct rk_screen *screen)
 {
        struct rk_lcdc_driver *dev_drv = rk_get_prmry_lcdc_drv();
-       return dev_drv->screen0;
+       memcpy(screen, dev_drv->screen0, sizeof(struct rk_screen));
+       return 0;
+       
 
 }
 
index 8a50ee68f81cab7e33be5e1501bd89dccbb06b94..dfa9be99ebf60937042a9b0ffdb5963efee6de79 100644 (file)
 #define ONE_DUAL       1
 #define DUAL           2
 
+#define OUT_P888            0  //24bit screen,connect to lcdc D0~D23
+#define OUT_P666            1  //18bit screen,connect to lcdc D0~D17
+#define OUT_P565            2
+#define OUT_S888x           4
+#define OUT_CCIR656         6
+#define OUT_S888            8
+#define OUT_S888DUMY        12
+#define OUT_P16BPP4         24
+#define OUT_D888_P666       0x21       //18bit screen,connect to lcdc D2~D7, D10~D15, D18~D23
+#define OUT_D888_P565       0x22
+
+#define SCREEN_NULL        0
+#define SCREEN_RGB        1
+#define SCREEN_LVDS       2
+#define SCREEN_DUAL_LVDS   3
+#define SCREEN_MCU         4
+#define SCREEN_TVOUT       5
+#define SCREEN_HDMI        6
+#define SCREEN_MIPI       7
+#define SCREEN_DUAL_MIPI   8
+#define SCREEN_EDP         9
+
+#define LVDS_8BIT_1     0
+#define LVDS_8BIT_2     1
+#define LVDS_8BIT_3     2
+#define LVDS_6BIT       3
+/*             lvds connect config       
+ *                                        
+ *             LVDS_8BIT_1    LVDS_8BIT_2     LVDS_8BIT_3     LVDS_6BIT
+----------------------------------------------------------------------
+       TX0     R0              R2              R2              R0
+       TX1     R1              R3              R3              R1
+       TX2     R2              R4              R4              R2
+Y      TX3     R3              R5              R5              R3
+0      TX4     R4              R6              R6              R4
+       TX6     R5              R7              R7              R5      
+       TX7     G0              G2              G2              G0
+----------------------------------------------------------------------
+       TX8     G1              G3              G3              G1
+       TX9     G2              G4              G4              G2
+Y      TX12    G3              G5              G5              G3
+1      TX13    G4              G6              G6              G4
+       TX14    G5              G7              G7              G5
+       TX15    B0              B2              B2              B0
+       TX18    B1              B3              B3              B1
+----------------------------------------------------------------------
+       TX19    B2              B4              B4              B2
+       TX20    B3              B5              B5              B3
+       TX21    B4              B6              B6              B4
+Y      TX22    B5              B7              B7              B5
+2      TX24    HSYNC           HSYNC           HSYNC           HSYNC
+       TX25    VSYNC           VSYNC           VSYNC           VSYNC
+       TX26    ENABLE          ENABLE          ENABLE          ENABLE
+----------------------------------------------------------------------    
+       TX27    R6              R0              GND             GND
+       TX5     R7              R1              GND             GND
+       TX10    G6              G0              GND             GND
+Y      TX11    G7              G1              GND             GND
+3      TX16    B6              B0              GND             GND
+       TX17    B7              B1              GND             GND
+       TX23    RSVD            RSVD            RSVD            RSVD
+----------------------------------------------------------------------
+*/
+
 #endif
index 7627817bf2b3370088e4d713ae8e507d35a83686..bf77050fe6f97f8679b3cc83e7b4fd15bfbbd9e2 100755 (executable)
@@ -354,7 +354,7 @@ extern int rk_fb_register(struct rk_lcdc_driver *dev_drv,
                                struct rk_lcdc_win *win, int id);
 extern int rk_fb_unregister(struct rk_lcdc_driver *dev_drv);
 extern struct rk_lcdc_driver *rk_get_lcdc_drv(char *name);
-extern struct rk_screen *rk_fb_get_prmry_screen(void);
+extern int rk_fb_get_prmry_screen( struct rk_screen *screen);
 extern u32 rk_fb_get_prmry_screen_pixclock(void);
 extern int rk_disp_pwr_ctr_parse_dt(struct rk_lcdc_driver *dev_drv);
 extern int rk_disp_pwr_enable(struct rk_lcdc_driver *dev_drv);
index 3ecaa16d149617c0fe6eafade360caa91f43668d..19e62306796f56c1fd3bd9473b509e1d10587905 100755 (executable)
@@ -1,58 +1,6 @@
 #ifndef _SCREEN_H
 #define _SCREEN_H
 
-#define LVDS_8BIT_1     0
-#define LVDS_8BIT_2     1
-#define LVDS_8BIT_3     2
-#define LVDS_6BIT       3
-/*             lvds connect config       
- *                                        
- *             LVDS_8BIT_1    LVDS_8BIT_2     LVDS_8BIT_3     LVDS_6BIT
-----------------------------------------------------------------------
-       TX0     R0              R2              R2              R0
-       TX1     R1              R3              R3              R1
-       TX2     R2              R4              R4              R2
-Y      TX3     R3              R5              R5              R3
-0      TX4     R4              R6              R6              R4
-       TX6     R5              R7              R7              R5      
-       TX7     G0              G2              G2              G0
-----------------------------------------------------------------------
-       TX8     G1              G3              G3              G1
-       TX9     G2              G4              G4              G2
-Y      TX12    G3              G5              G5              G3
-1      TX13    G4              G6              G6              G4
-       TX14    G5              G7              G7              G5
-       TX15    B0              B2              B2              B0
-       TX18    B1              B3              B3              B1
-----------------------------------------------------------------------
-       TX19    B2              B4              B4              B2
-       TX20    B3              B5              B5              B3
-       TX21    B4              B6              B6              B4
-Y      TX22    B5              B7              B7              B5
-2      TX24    HSYNC           HSYNC           HSYNC           HSYNC
-       TX25    VSYNC           VSYNC           VSYNC           VSYNC
-       TX26    ENABLE          ENABLE          ENABLE          ENABLE
-----------------------------------------------------------------------    
-       TX27    R6              R0              GND             GND
-       TX5     R7              R1              GND             GND
-       TX10    G6              G0              GND             GND
-Y      TX11    G7              G1              GND             GND
-3      TX16    B6              B0              GND             GND
-       TX17    B7              B1              GND             GND
-       TX23    RSVD            RSVD            RSVD            RSVD
-----------------------------------------------------------------------
-*/
-
-typedef enum _SCREEN_TYPE {
-       SCREEN_NULL = 0,
-       SCREEN_RGB,
-       SCREEN_LVDS,
-       SCREEN_MCU,
-       SCREEN_TVOUT,
-       SCREEN_HDMI,
-       SCREEN_MIPI,
-} SCREEN_TYPE;
-
 typedef enum _REFRESH_STAGE {
     REFRESH_PRE = 0,
     REFRESH_END,
index 5d0259b08e015ae0e3d288de561446cc995aecdb..e7a4db4b1347ff83de6eec5a2c9cc34b36d592af 100644 (file)
@@ -27,6 +27,11 @@ enum display_flags {
        DISPLAY_FLAGS_PIXDATA_NEGEDGE   = BIT(7),
        DISPLAY_FLAGS_INTERLACED        = BIT(8),
        DISPLAY_FLAGS_DOUBLESCAN        = BIT(9),
+#if defined(CONFIG_FB_ROCKCHIP)
+       DISPLAY_FLAGS_SWAP_GB           = BIT(10),
+       DISPLAY_FLAGS_SWAP_RG           = BIT(11),
+       DISPLAY_FLAGS_SWAP_RB           = BIT(12),
+#endif
 };
 
 /*
@@ -70,6 +75,11 @@ struct display_timing {
        struct timing_entry vsync_len;          /* ver. sync len */
 
        enum display_flags flags;               /* display flags */
+#if defined(CONFIG_FB_ROCKCHIP)
+       u16 screen_type;                        /*screen type*/
+       u16 lvds_format;                        /*lvds data format for lvds screen*/
+       u16 face;                               /*display output  interface format:24bit 18bit 16bit*/
+#endif
 };
 
 /*