UPSTREAM: PCI: rockchip: Increase the Max Credit update interval.

This increases the likelihood of link state to automatically go to L1
and save some power.

The default credit update interval of 7.5 us results in the rootport
sending UpdateFC-P and UpdateFC-NP packets too often, thus resulting
in the link never going to L1, and always staying in L0/L0s. The
value 24 us was chosen after some experiments and peeking over the
PCIe bus to see that we do enter L1 substate when there is not enough
traffic on the PCIe bus.

Change-Id: I23eccba98f6fe731bcacec80349dc05bd7baf9c1
Signed-off-by: Rajat Jain <rajatja@google.com>
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
(cherry picked from git.kernel.org/cgit/linux/kernel/git/next/linux-next.git
commit 277743ef616defc870d101f9cf9d3488aba1c1b6)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 8bedc1e1ef80753c57fe05e8639064943ecf82b8..91f6fa2811491b9f2d85c1ebdc69fefd6b8abda2 100644 (file)
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -95,6 +95,11 @@
 #define   PCIE_CORE_PL_CONF_SPEED_MASK         0x00000018
 #define   PCIE_CORE_PL_CONF_LANE_MASK          0x00000006
 #define   PCIE_CORE_PL_CONF_LANE_SHIFT         1
+#define PCIE_CORE_TXCREDIT_CFG1                (PCIE_CORE_CTRL_MGMT_BASE + 0x020)
+#define   PCIE_CORE_TXCREDIT_CFG1_MUI_MASK     0xFFFF0000
+#define   PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT    16
+#define   PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(x) \
+               (((x) >> 3) << PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT)
 #define PCIE_CORE_INT_STATUS           (PCIE_CORE_CTRL_MGMT_BASE + 0x20c)
 #define   PCIE_CORE_INT_PRFPE                  BIT(0)
 #define   PCIE_CORE_INT_CRFPE                  BIT(1)
@@ -224,6 +229,17 @@ static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
        rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
 }
 
+static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
+{
+       u32 val;
+
+       /* Update Tx credit maximum update interval */
+       val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1);
+       val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK;
+       val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000);       /* ns */
+       rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
+}
+
 static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
                                      struct pci_bus *bus, int dev)
 {
@@ -597,6 +613,7 @@ static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
                rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
        } else if (reg & PCIE_CLIENT_INT_PHY) {
                dev_dbg(dev, "phy link changes\n");
+               rockchip_pcie_update_txcredit_mui(rockchip);
                rockchip_pcie_clr_bw_int(rockchip);
        }