ddr_rk32.c: set dclk_div to 64(down dclk) when ddr change rate

Signed-off-by: 陈亮 <cl@rock-chips.com>

diff --git a/arch/arm/mach-rockchip/ddr_rk32.c b/arch/arm/mach-rockchip/ddr_rk32.c
index 4fad0476deab481a543f9a4fc53dbeb2c469256e..4ce3220f7df0c1a20570c948e719003b885a584d 100755 (executable)
--- a/arch/arm/mach-rockchip/ddr_rk32.c
+++ b/arch/arm/mach-rockchip/ddr_rk32.c
@@ -3655,8 +3655,8 @@ static noinline uint32 ddr_change_freq_sram(void *arg)
     uint32 gpllvaluel;
     freq_t *p_freq_t=(freq_t *)arg;    
     uint32 nMHz=p_freq_t->nMHz;
-       struct rk_screen screen;
-       int dclk_div = 0;
+       static struct rk_screen screen;
+       static int dclk_div, down_dclk_div;
 
 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
     struct ddr_freq_t *p_ddr_freq_t=p_freq_t->p_ddr_freq_t;
@@ -3669,13 +3669,14 @@ static noinline uint32 ddr_change_freq_sram(void *arg)
         freq_slew = (nMHz>ddr_freq)? 1 : 0;
     }
 #endif
-
-       rk_fb_get_prmry_screen(&screen);
-       if (screen.lcdc_id == 0)
-               dclk_div = (cru_readl(RK3288_CRU_CLKSELS_CON(27)) >> 8) & 0xff;
-       else if (screen.lcdc_id == 1)
-               dclk_div = (cru_readl(RK3288_CRU_CLKSELS_CON(29)) >> 8) & 0xff;
-
+       if (!screen.mode.pixclock) {
+               rk_fb_get_prmry_screen(&screen);
+               if (screen.lcdc_id == 0)
+                       dclk_div = (cru_readl(RK3288_CRU_CLKSELS_CON(27)) >> 8) & 0xff;
+               else if (screen.lcdc_id == 1)
+                       dclk_div = (cru_readl(RK3288_CRU_CLKSELS_CON(29)) >> 8) & 0xff;
+               down_dclk_div = 64*(dclk_div+1)-1;
+       }
     param.arm_freq = ddr_get_pll_freq(APLL);
     gpllvaluel = ddr_get_pll_freq(GPLL);
     if((200 < gpllvaluel) ||( gpllvaluel <1600))      //GPLL:200MHz~1600MHz
@@ -3750,11 +3751,11 @@ static noinline uint32 ddr_change_freq_sram(void *arg)
     param.dqstr_value = dqstr_value;
        rk_fb_set_prmry_screen_status(SCREEN_PREPARE_DDR_CHANGE);
        if (screen.lcdc_id == 0)
-               cru_writel(0 | CRU_W_MSK_SETBITS(0xff, 8, 0xff),
-               RK3288_CRU_CLKSELS_CON(27));
+               cru_writel(0 | CRU_W_MSK_SETBITS(down_dclk_div, 8, 0xff),
+                          RK3288_CRU_CLKSELS_CON(27));
        else if (screen.lcdc_id == 1)
-               cru_writel(0 | CRU_W_MSK_SETBITS(0xff, 8, 0xff),
-               RK3288_CRU_CLKSELS_CON(29));
+               cru_writel(0 | CRU_W_MSK_SETBITS(down_dclk_div, 8, 0xff),
+                          RK3288_CRU_CLKSELS_CON(29));
 
     call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_change_freq_sram)),
                     &param,