clk: rockchip: add clock ids for mpll_src and 32k on RK3366

Set the newly added id for mpll_src and 32k, so that they can be called
in other parts.

Change-Id: Ief82231215a147b62abcfbb5565054470fc9ea37
Signed-off-by: Feng Xiao <xf@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-rk3366.c b/drivers/clk/rockchip/clk-rk3366.c
index fb45fcac947d9530f7bfeedc18fb9023dc33df0c..4c892a6224e64c54ca9336ccc700425f14d98fcb 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3366.c
+++ b/drivers/clk/rockchip/clk-rk3366.c
@@ -94,7 +94,7 @@ PNAME(mux_pll_src_cpll_gpll_npll_usb_p) = { "cpll", "gpll", "npll",
                                            "usbphy_480m" };
 PNAME(mux_pll_src_cpll_gpll_npll_mpll_p) = { "cpll", "gpll", "npll", "mpll_src" };
 PNAME(mux_vop_full_pwm_p) = { "xin24m", "cpll", "gpll", "npll" };
-PNAME(mux_clk_32k_p)           = { "xin32k", "clk_32k_inter" };
+PNAME(mux_clk_32k_p)           = { "xin32k", "clk_32k_intr" };
 PNAME(mux_i2s_8ch_pre_p)       = { "i2s_8ch_src", "i2s_8ch_frac",
                                    "ext_i2s", "xin12m" };
 PNAME(mux_i2s_8ch_clkout_p)    = { "i2s_8ch_pre", "xin12m" };
@@ -221,7 +221,7 @@ static struct rockchip_clk_branch rk3366_clk_branches[] __initdata = {
         * Clock-Architecture Diagram 1
         */
 
-       GATE(0, "mpll_src", "mpll", CLK_IGNORE_UNUSED,
+       GATE(SCLK_MPLL_SRC, "mpll_src", "mpll", CLK_IGNORE_UNUSED,
                        RK3368_CLKGATE_CON(2), 11, GFLAGS),
 
        /*
@@ -231,9 +231,9 @@ static struct rockchip_clk_branch rk3366_clk_branches[] __initdata = {
        MUX(SCLK_USBPHY480M, "usbphy_480m", mux_usbphy480m_p, 0,
                        RK3368_CLKSEL_CON(13), 6, 1, MFLAGS),
 
-       DIV(0, "clk_32k_inter", "xin24m", 0,
+       DIV(SCLK_32K_INTR, "clk_32k_intr", "xin24m", 0,
                        RK3368_CLKSEL_CON(7), 0, 10, DFLAGS),
-       MUX(0, "clk_32k", mux_clk_32k_p, CLK_SET_RATE_PARENT,
+       MUX(SCLK_32K, "clk_32k", mux_clk_32k_p, CLK_SET_RATE_PARENT,
                        RK3368_CLKSEL_CON(7), 15, 1, MFLAGS),
 
        GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,

diff --git a/include/dt-bindings/clock/rk3366-cru.h b/include/dt-bindings/clock/rk3366-cru.h
index f3d99b854e39d111f35b7d46905a566a881210eb..9facbd51c1e32c44a1179bfac144e25fbbc8be23 100644 (file)
--- a/include/dt-bindings/clock/rk3366-cru.h
+++ b/include/dt-bindings/clock/rk3366-cru.h
@@ -93,6 +93,9 @@
 #define SCLK_VIP_SRC           127
 #define SCLK_VIP_OUT           128
 #define SCLK_PVTM_PMU          129
+#define SCLK_MPLL_SRC          130
+#define SCLK_32K_INTR          131
+#define SCLK_32K               132
 
 #define DCLK_VOP_FULL          170
 #define DCLK_VOP_LITE          171