clk: rockchip: rk3368: remove the flag ROCKCHIP_PLL_SYNC_RATE for NPLL

NPLL is used for vop dclk, sync rate flag would cause loader display
abnormal.

Change-Id: Ia170a8d0b7d1f39e2c9dcbc10b5d33fd1886d5f7
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index d4026aebb238d0361d8fedf650d48e156ea235b7..279c72b59b67f849c79eb44f6d8df5ea78999500 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -147,7 +147,7 @@ static struct rockchip_pll_clock rk3368_pll_clks[] __initdata = {
        [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3368_PLL_CON(16),
                     RK3368_PLL_CON(19), 8, 4, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
        [npll] = PLL(pll_rk3066, PLL_NPLL, "npll",  mux_pll_p, 0, RK3368_PLL_CON(20),
-                    RK3368_PLL_CON(23), 8, 5, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
+                    RK3368_PLL_CON(23), 8, 5, 0, rk3368_pll_rates),
 };
 
 static struct clk_div_table div_ddrphy_t[] = {