arm64: dts: rockchip: rk3399-evb: merge common part
authorHuang, Tao <huangtao@rock-chips.com>
Fri, 15 Jul 2016 06:38:37 +0000 (14:38 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Fri, 15 Jul 2016 06:47:57 +0000 (14:47 +0800)
dtbs is same as before.

Change-Id: I0381607627905b98dee7962f8e62844c877fcd54
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
arch/arm64/boot/dts/rockchip/rk3399-evb-rev1.dtsi
arch/arm64/boot/dts/rockchip/rk3399-evb-rev2.dtsi
arch/arm64/boot/dts/rockchip/rk3399-evb.dtsi

index 2d68c158d6d398370f15cffdd9fbcc8f7041f381..9a609d77dfa1a7c73f36c4cc3ed615024420fc45 100644 (file)
        };
 };
 
-&cpu_l0 {
-       cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l1 {
-       cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l2 {
-       cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l3 {
-       cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_b0 {
-       cpu-supply = <&vdd_cpu_b>;
-};
-
-&cpu_b1 {
-       cpu-supply = <&vdd_cpu_b>;
-};
-
-&gpu {
-       status = "okay";
-       mali-supply = <&vdd_gpu>;
-};
-
 &pwm2 {
        status = "okay";
 };
-
index 0d6bd161635e8499a31ed836badbd25a1bcc079d..1d1f41063f8105901f52a9f47d1e376d669cfc0c 100644 (file)
                };
        };
 };
-
-&cpu_l0 {
-       cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l1 {
-       cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l2 {
-       cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l3 {
-       cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_b0 {
-       cpu-supply = <&vdd_cpu_b>;
-};
-
-&cpu_b1 {
-       cpu-supply = <&vdd_cpu_b>;
-};
-
-&gpu {
-       status = "okay";
-       mali-supply = <&vdd_gpu>;
-};
-
index 7e3f588cc0880181db1178297a48a4fee1a65a45..0523746eda36ed956d6f88d160225de7b2851b12 100644 (file)
        };
 };
 
+&cpu_l0 {
+       cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+       cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+       cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+       cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+       cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+       cpu-supply = <&vdd_cpu_b>;
+};
+
+&gpu {
+       status = "okay";
+       mali-supply = <&vdd_gpu>;
+};
+
 &sdmmc {
        clock-frequency = <150000000>;
        clock-freq-min-max = <400000 150000000>;
        i2c-scl-falling-time-ns = <15>;
 };
 
+&i2c1 {
+       status = "okay";
+       i2c-scl-rising-time-ns = <300>;
+       i2c-scl-falling-time-ns = <15>;
+
+       es8316: es8316@10 {
+               #sound-dai-cells = <0>;
+               compatible = "everest,es8316";
+               reg = <0x10>;
+               clocks = <&cru SCLK_I2S_8CH_OUT>;
+               clock-names = "mclk";
+               spk-con-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+               hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>;
+       };
+};
+
 &i2c4 {
        status = "okay";
        i2c-scl-rising-time-ns = <600>;
        };
 };
 
-&i2c1 {
-       status = "okay";
-       i2c-scl-rising-time-ns = <300>;
-       i2c-scl-falling-time-ns = <15>;
-
-       es8316: es8316@10 {
-               #sound-dai-cells = <0>;
-               compatible = "everest,es8316";
-               reg = <0x10>;
-               clocks = <&cru SCLK_I2S_8CH_OUT>;
-               clock-names = "mclk";
-               spk-con-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
-               hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>;
-       };
-};
-
 &pcie0 {
        assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
        assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;