ARM64: dts: rk3366: assign rates for aclk_bus and aclk_peri

Assign rates for aclk_bus and aclk_peri according to our original design.

Change-Id: Iab4961d485421151be5dbdacf6929800150ab342
Signed-off-by: Feng Xiao <xf@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3366.dtsi b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
index a9b6bc7551d523326ac81edcc05a90c7f545691e..6591a47b118d2b4118a0830c66d7df89bc6b1b95 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3366.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
@@ -668,7 +668,9 @@
                        <&cru PLL_NPLL>, <&cru PLL_MPLL>,
                        <&cru PLL_WPLL>, <&cru PLL_BPLL>,
                        <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
-                       <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>;
+                       <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>,
+                       <&cru ACLK_BUS>, <&cru ACLK_PERI0>,
+                       <&cru ACLK_PERI1>;
                assigned-clock-rates =
                        <0>,
                        <0>, <0>,
@@ -676,7 +678,9 @@
                        <594000000>, <594000000>,
                        <960000000>, <520000000>,
                        <375000000>, <288000000>,
-                       <100000000>, <100000000>;
+                       <100000000>, <100000000>,
+                       <288000000>, <288000000>,
+                       <144000000>;
                assigned-clock-parents =
                        <&cru SCLK_32K_INTR>,
                        <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>;