clk: rockchip: rk3399: add 106.5MHz clock configuration for 1440x900

Change-Id: I49331fdbf595b731f64f34beb25e817c502984fe
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 62a7f5bb74c5e54c2d4fa1b8e5d0f80724d3b2c2..f4f614a53a099c9624bab8a89b2e3355c4fb1f1c 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -100,6 +100,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
        RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0),
        RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
        RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0),
+       RK3036_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0),
        RK3036_PLL_RATE(  96000000, 1, 64, 4, 4, 1, 0),
        RK3036_PLL_RATE(  74250000, 2, 99, 4, 4, 1, 0),
        RK3036_PLL_RATE(  65000000, 1, 65, 6, 4, 1, 0),
@@ -116,6 +117,7 @@ static struct rockchip_pll_rate_table rk3399_vpll_rates[] = {
        RK3036_PLL_RATE( 296703297, 1, 123, 5, 2, 0, 10508807),  /* vco = 2967032970 */
        RK3036_PLL_RATE( 148500000, 1, 129, 7, 3, 0, 15728640),  /* vco = 3118500000 */
        RK3036_PLL_RATE( 148351648, 1, 123, 5, 4, 0, 10508800),  /* vco = 2967032960 */
+       RK3036_PLL_RATE( 106500000, 1, 124, 7, 4, 0,  4194304),  /* vco = 2982000000 */
        RK3036_PLL_RATE(  74250000, 1, 129, 7, 6, 0, 15728640),  /* vco = 3118500000 */
        RK3036_PLL_RATE(  74175824, 1, 129, 7, 6, 0, 13550823),  /* vco = 3115384608 */
        RK3036_PLL_RATE(  65000000, 1, 113, 7, 6, 0, 12582912),  /* vco = 2730000000 */