rk3368: usb: reset usb phy when channel halt

Signed-off-by: lyz <lyz@rock-chips.com>

diff --git a/drivers/usb/dwc_otg_310/dwc_otg_hcd_intr.c b/drivers/usb/dwc_otg_310/dwc_otg_hcd_intr.c
index 22a118efeae7e12146983c0eed9ac64871674d91..f462accd82e10b5e4b245b6377d6be39b97949dc 100755 (executable)
--- a/drivers/usb/dwc_otg_310/dwc_otg_hcd_intr.c
+++ b/drivers/usb/dwc_otg_310/dwc_otg_hcd_intr.c
@@ -35,6 +35,8 @@
 #include "dwc_otg_hcd.h"
 #include "dwc_otg_regs.h"
 #include <linux/usb.h>
+#include "dwc_otg_driver.h"
+#include "usbdev_rk.h"
 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35)
 #include <../drivers/usb/core/hcd.h>
 #else
@@ -1922,6 +1924,7 @@ static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t *hcd,
        hcint_data_t hcint;
        hcintmsk_data_t hcintmsk;
        int out_nak_enh = 0;
+       struct dwc_otg_platform_data *pldata = hcd->core_if->otg_dev->pldata;
 
        /* For core with OUT NAK enhancement, the flow for high-
         * speed CONTROL/BULK OUT is handled a little differently.
@@ -2049,6 +2052,8 @@ static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t *hcd,
        } else {
                DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n",
                           hcint.d32);
+               pldata->soft_reset(pldata, RST_CHN_HALT);
+               mdelay(5);
                if (!hcint.b.nyet && !hcint.b.nak && !hcint.b.ack)
                        clear_hc_int(hc_regs, chhltd);
        }

diff --git a/drivers/usb/dwc_otg_310/usbdev_rk3368.c b/drivers/usb/dwc_otg_310/usbdev_rk3368.c
index 8b24096aec6eec1db90020fa93fe88aaeea725e3..dd5771d228e00686182630741413172c661e608d 100644 (file)
--- a/drivers/usb/dwc_otg_310/usbdev_rk3368.c
+++ b/drivers/usb/dwc_otg_310/usbdev_rk3368.c
@@ -79,7 +79,16 @@ static void usb20otg_soft_reset(void *pdata, enum rkusb_rst_flag rst_type)
                reset_control_deassert(rst_otg_c);
                reset_control_deassert(rst_otg_h);
                break;
-
+       case RST_CHN_HALT:
+               /* PHY reset */
+               uoc_write(UOC_HIWORD_UPDATE(0x1, 0x3, 0), 0x700);
+               reset_control_assert(rst_otg_p);
+               udelay(15);
+               uoc_write(UOC_HIWORD_UPDATE(0x2, 0x3, 0), 0x700);
+               udelay(1500);
+               reset_control_deassert(rst_otg_p);
+               udelay(2);
+               break;
        default:
                break;
        }