clk: rockchip: update dt-binding header for rk3399 some clock IDs

Add some clock IDs for driver reference them.

Change-Id: I43b2507a58f141f8e04a530b5e43db507097f301
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h
index 5f13f49df6926af4ca461f87133c0595f853bd6d..914dc5ab74837c326636dd99cca5ffbcb362e56d 100644 (file)
--- a/include/dt-bindings/clock/rk3399-cru.h
+++ b/include/dt-bindings/clock/rk3399-cru.h
@@ -78,7 +78,7 @@
 #define SCLK_ISP1                      111
 #define SCLK_HDMI_CEC                  112
 #define SCLK_HDMI_SFR                  113
-#define SCLK_DP_CORE_SRC               114
+#define SCLK_DP_CORE                   114
 #define SCLK_PVTM_CORE_L               115
 #define SCLK_PVTM_CORE_B               116
 #define SCLK_PVTM_GPU                  117
@@ -104,7 +104,7 @@
 #define SCLK_CIF_OUT                   137
 #define SCLK_PCIEPHY_REF               138
 #define SCLK_PCIE_CORE                 139
-#define SCLK_MO_PERILP                 140
+#define SCLK_M0_PERILP                 140
 #define SCLK_M0_PERILP_DEC             141
 #define SCLK_CM0S                      142
 #define SCLK_DBG_NOC                   143
@@ -122,9 +122,18 @@
 #define SCLK_SDMMC_SAMPLE              155
 #define SCLK_SDIO_DRV                  156
 #define SCLK_SDIO_SAMPLE               157
-
-#define DCLK_VOP0                      170
-#define DCLK_VOP1                      171
+#define SCLK_VDU_CORE                  158
+#define SCLK_VDU_CA                    159
+#define SCLK_PCIE_PM                   160
+#define SCLK_SPDIF_REC_DPTX            161
+#define SCLK_DPHY_PLL                  162
+#define SCLK_DPHY_TX0_CFG              163
+#define SCLK_DPHY_TX1RX1_CFG           164
+#define SCLK_DPHY_RX0_CFG              165
+
+#define DCLK_VOP0                      180
+#define DCLK_VOP1                      181
+#define DCLK_M0_PERILP                 182
 
 /* aclk gates */
 #define ACLK_PERIHP                    192
@@ -191,6 +200,12 @@
 #define ACLK_GIC_ADB400_CORE_B_2_GIC   253
 #define ACLK_GIC_ADB400_GIC_2_CORE_L   254
 #define ACLK_GIC_ADB400_GIC_2_CORE_B   255
+#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256
+#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257
+#define ACLK_ADB400M_PD_CORE_L         258
+#define ACLK_ADB400M_PD_CORE_B         259
+#define ACLK_PERF_CORE_L               260
+#define ACLK_PERF_CORE_B               261
 
 /* pclk gates */
 #define PCLK_PERIHP                    320
@@ -258,6 +273,11 @@
 #define PCLK_EFUSE1024S                        382
 #define PCLK_PMU_INTR_ARB              383
 #define PCLK_MAILBOX0                  384
+#define PCLK_USBPHY_MUX_G              385
+#define PCLK_UPHY0_TCPHY_G             386
+#define PCLK_UPHY0_TCPD_G              387
+#define PCLK_UPHY1_TCPHY_G             388
+#define PCLK_UPHY1_TCPD_G              389
 
 /* hclk gates */
 #define HCLK_PERIHP                    448