clk: imx6: initialize GPU clocks

commit d8846023aed1293e54d33499558fc2aa2b2f393f upstream.

Initialize the GPU clock muxes to sane inputs. Until now they have
not been changed from their default values, which means that both
GPU3D shader and GPU2D core were fed by clock inputs whose rates
exceed the maximium allowed frequency of the cores by as much as
200MHz.

This fixes a severe GPU stability issue on i.MX6DL.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index c1935081d34aee3403d0ee5d6904b117bd5dfa12..aab64205d8663b8233a43491d4ce1cb722191ba1 100644 (file)
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -550,6 +550,24 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        if (IS_ENABLED(CONFIG_PCI_IMX6))
                clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]);
 
+       /*
+        * Initialize the GPU clock muxes, so that the maximum specified clock
+        * rates for the respective SoC are not exceeded.
+        */
+       if (clk_on_imx6dl()) {
+               clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL],
+                              clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
+               clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL],
+                              clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
+       } else if (clk_on_imx6q()) {
+               clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL],
+                              clk[IMX6QDL_CLK_MMDC_CH0_AXI]);
+               clk_set_parent(clk[IMX6QDL_CLK_GPU3D_SHADER_SEL],
+                              clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
+               clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL],
+                              clk[IMX6QDL_CLK_PLL3_USB_OTG]);
+       }
+
        imx_register_uart_clocks(uart_clks);
 }
 CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);