};
rga: rga@1010c000 {
- compatible = "rockchip,rga";
+ compatible = "rockchip,rga_drv";
reg = <0x1010c000 0x1000>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates0 11>, <&clk_gates1 4>;
#define _RGA_DRIVER_H_\r
\r
#include <linux/mutex.h>\r
+#include <linux/scatterlist.h>\r
+\r
\r
#define RGA_BLIT_SYNC 0x5017\r
#define RGA_BLIT_ASYNC 0x5018\r
\r
\r
#define RGA_REG_CTRL_LEN 0x8 /* 8 */\r
-#define RGA_REG_CMD_LEN 0x1c /* 28 */\r
+#define RGA_REG_CMD_LEN 0x20 /* 32 */\r
#define RGA_CMD_BUF_SIZE 0x700 /* 16*28*4 */\r
\r
#define RGA_OUT_OF_RESOURCES -10\r
\r
/* RGA process mode enum */\r
enum\r
-{ \r
+{\r
bitblt_mode = 0x0,\r
color_palette_mode = 0x1,\r
color_fill_mode = 0x2,\r
\r
\r
/* RGA rotate mode */\r
-enum \r
+enum\r
{\r
rotate_mode0 = 0x0, /* no rotate */\r
rotate_mode1 = 0x1, /* rotate */\r
\r
\r
/*\r
-// Alpha Red Green Blue \r
-{ 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGBA }, // RK_FORMAT_RGBA_8888 \r
-{ 4, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGBX_8888 \r
+// Alpha Red Green Blue\r
+{ 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGBA }, // RK_FORMAT_RGBA_8888\r
+{ 4, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGBX_8888\r
{ 3, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGB_888\r
{ 4, 32, {{32,24, 24,16, 16, 8, 8, 0 }}, GGL_BGRA }, // RK_FORMAT_BGRA_8888\r
-{ 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // RK_FORMAT_RGB_565 \r
-{ 2, 16, {{ 1, 0, 16,11, 11, 6, 6, 1 }}, GGL_RGBA }, // RK_FORMAT_RGBA_5551 \r
+{ 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // RK_FORMAT_RGB_565\r
+{ 2, 16, {{ 1, 0, 16,11, 11, 6, 6, 1 }}, GGL_RGBA }, // RK_FORMAT_RGBA_5551\r
{ 2, 16, {{ 4, 0, 16,12, 12, 8, 8, 4 }}, GGL_RGBA }, // RK_FORMAT_RGBA_4444\r
{ 3, 24, {{ 0, 0, 24,16, 16, 8, 8, 0 }}, GGL_BGR }, // RK_FORMAT_BGB_888\r
\r
RK_FORMAT_RGBA_5551 = 0x5,\r
RK_FORMAT_RGBA_4444 = 0x6,\r
RK_FORMAT_BGR_888 = 0x7,\r
- \r
- RK_FORMAT_YCbCr_422_SP = 0x8, \r
- RK_FORMAT_YCbCr_422_P = 0x9, \r
- RK_FORMAT_YCbCr_420_SP = 0xa, \r
+\r
+ RK_FORMAT_YCbCr_422_SP = 0x8,\r
+ RK_FORMAT_YCbCr_422_P = 0x9,\r
+ RK_FORMAT_YCbCr_420_SP = 0xa,\r
RK_FORMAT_YCbCr_420_P = 0xb,\r
\r
- RK_FORMAT_YCrCb_422_SP = 0xc, \r
- RK_FORMAT_YCrCb_422_P = 0xd, \r
- RK_FORMAT_YCrCb_420_SP = 0xe, \r
+ RK_FORMAT_YCrCb_422_SP = 0xc,\r
+ RK_FORMAT_YCrCb_422_P = 0xd,\r
+ RK_FORMAT_YCrCb_420_SP = 0xe,\r
RK_FORMAT_YCrCb_420_P = 0xf,\r
- \r
+\r
RK_FORMAT_BPP1 = 0x10,\r
RK_FORMAT_BPP2 = 0x11,\r
RK_FORMAT_BPP4 = 0x12,\r
RK_FORMAT_BPP8 = 0x13,\r
};\r
- \r
- \r
+\r
+\r
typedef struct rga_img_info_t\r
{\r
unsigned int yrgb_addr; /* yrgb mem addr */\r
unsigned int uv_addr; /* cb/cr mem addr */\r
unsigned int v_addr; /* cr mem addr */\r
unsigned int format; //definition by RK_FORMAT\r
- \r
+\r
unsigned short act_w;\r
unsigned short act_h;\r
unsigned short x_offset;\r
unsigned short y_offset;\r
- \r
+\r
unsigned short vir_w;\r
unsigned short vir_h;\r
- \r
+\r
unsigned short endian_mode; //for BPP\r
unsigned short alpha_swap;\r
}\r
{\r
unsigned short xmin;\r
unsigned short xmax; // width - 1\r
- unsigned short ymin; \r
- unsigned short ymax; // height - 1 \r
+ unsigned short ymin;\r
+ unsigned short ymax; // height - 1\r
} RECT;\r
\r
typedef struct RGB\r
\r
struct rga_req {\r
uint8_t render_mode; /* (enum) process mode sel */\r
- \r
+\r
rga_img_info_t src; /* src image info */\r
rga_img_info_t dst; /* dst image info */\r
rga_img_info_t pat; /* patten image info */\r
\r
uint32_t rop_mask_addr; /* rop4 mask addr */\r
uint32_t LUT_addr; /* LUT addr */\r
- \r
+\r
RECT clip; /* dst clip window default value is dst_vir */\r
/* value from [0, w-1] / [0, h-1]*/\r
- \r
+\r
int32_t sina; /* dst angle default value 0 16.16 scan from table */\r
- int32_t cosa; /* dst angle default value 0 16.16 scan from table */ \r
+ int32_t cosa; /* dst angle default value 0 16.16 scan from table */\r
\r
uint16_t alpha_rop_flag; /* alpha rop process flag */\r
/* ([0] = 1 alpha_rop_enable) */\r
- /* ([1] = 1 rop enable) */ \r
+ /* ([1] = 1 rop enable) */\r
/* ([2] = 1 fading_enable) */\r
/* ([3] = 1 PD_enable) */\r
/* ([4] = 1 alpha cal_mode_sel) */\r
/* ([6] = 1 gradient fill mode sel) */\r
/* ([7] = 1 AA_enable) */\r
\r
- uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */ \r
- \r
+ uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */\r
+\r
uint32_t color_key_max; /* color key max */\r
- uint32_t color_key_min; /* color key min */ \r
+ uint32_t color_key_min; /* color key min */\r
\r
uint32_t fg_color; /* foreground color */\r
uint32_t bg_color; /* background color */\r
\r
COLOR_FILL gr_color; /* color fill use gradient */\r
- \r
+\r
line_draw_t line_draw_info;\r
- \r
+\r
FADING fading;\r
- \r
+\r
uint8_t PD_mode; /* porter duff alpha mode sel */\r
- \r
+\r
uint8_t alpha_global_value; /* global alpha value */\r
- \r
+\r
uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/\r
- \r
+\r
uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/\r
- \r
+\r
uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/\r
\r
- uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ \r
- \r
+ uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */\r
+\r
uint8_t endian_mode; /* 0/big endian 1/little endian*/\r
\r
uint8_t rotate_mode; /* (enum) rotate mode */\r
/* 0x3, y_mirror */\r
\r
uint8_t color_fill_mode; /* 0 solid color / 1 patten color */\r
- \r
+\r
MMU mmu_info; /* mmu information */\r
\r
uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */\r
/* ([4] zero mode en) */\r
/* ([5] dst alpha mode) */\r
\r
- uint8_t src_trans_mode; \r
+ uint8_t src_trans_mode;\r
+\r
+ struct sg_table *sg_src;\r
+ struct sg_table *sg_dst;\r
};\r
\r
- \r
+\r
typedef struct TILE_INFO\r
{\r
int64_t matrix[4];\r
- \r
+\r
uint16_t tile_x_num; /* x axis tile num / tile size is 8x8 pixel */\r
uint16_t tile_y_num; /* y axis tile num */\r
\r
int32_t y_dy;\r
\r
mdp_img_act dst_ctrl;\r
- \r
+\r
}\r
-TILE_INFO; \r
+TILE_INFO;\r
\r
\r
/**\r
atomic_t num_done;\r
} rga_session;\r
\r
-struct rga_reg { \r
+struct rga_reg {\r
rga_session *session;\r
struct list_head session_link; /* link to rga service session */\r
struct list_head status_link; /* link to register set list */\r
uint32_t sys_reg[RGA_REG_CTRL_LEN];\r
uint32_t cmd_reg[RGA_REG_CMD_LEN];\r
- \r
+\r
uint32_t *MMU_base;\r
- //atomic_t int_enable; \r
+ //atomic_t int_enable;\r
\r
//struct rga_req req;\r
};\r
struct list_head done; /* link to link_reg in struct vpu_reg */\r
struct list_head session; /* link to list_session in struct vpu_session */\r
atomic_t total_running;\r
- \r
+\r
struct rga_reg *reg;\r
- \r
+\r
uint32_t cmd_buff[28*8];/* cmd_buff for rga */\r
uint32_t *pre_scale_buf;\r
atomic_t int_disable; /* 0 int enable 1 int disable */\r
\r
\r
\r
-#if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026)\r
+#if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026) || defined(CONFIG_ARCH_RK312x)\r
#define RGA_BASE 0x1010c000\r
#elif defined(CONFIG_ARCH_RK30)\r
#define RGA_BASE 0x10114000\r
#define RGA_DST_VIR_INFO 0x150\r
\r
#define RGA_DST_CTR_INFO 0x154\r
-#define RGA_LINE_DRAW_XY_INFO 0x154 //repeat \r
+#define RGA_LINE_DRAW_XY_INFO 0x154 //repeat\r
\r
//Alpha/ROP Registers\r
#define RGA_ALPHA_CON 0x158\r
\r
#define RGA_MMU_TBL 0x16c //repeat\r
\r
+#define RGA_YUV_OUT_CFG 0x170\r
+#define RGA_DST_UV_MST 0x174\r
+\r
\r
#define RGA_BLIT_COMPLETE_EVENT 1\r
\r
long rga_ioctl_kernel(struct rga_req *req);\r
\r
-\r
#endif /*_RK29_IPP_DRIVER_H_*/\r
\r
rga_session rga_session_global;\r
\r
+long (*rga_ioctl_kernel_p)(struct rga_req *);\r
+\r
+\r
struct rga_drvdata {\r
struct miscdevice miscdev;\r
struct device dev;\r
req->src.act_w, req->src.act_h, req->src.vir_w, req->src.vir_h);\r
printk("src : x_off = %.8x y_off = %.8x\n", req->src.x_offset, req->src.y_offset);\r
\r
- printk("dst : yrgb_addr = %.8x, dst.uv_addr = %.8x, dst.v_addr = %.8x\n",\r
- req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr);\r
+ printk("dst : yrgb_addr = %.8x, dst.uv_addr = %.8x, dst.v_addr = %.8x, format = %d\n",\r
+ req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr, req->dst.format);\r
printk("dst : x_off = %.8x y_off = %.8x\n", req->dst.x_offset, req->dst.y_offset);\r
printk("dst : act_w = %d, act_h = %d, vir_w = %d, vir_h = %d\n",\r
req->dst.act_w, req->dst.act_h, req->dst.vir_w, req->dst.vir_h);\r
atomic_add(1, &rga_service.cmd_num);\r
atomic_add(1, ®->session->task_running);\r
\r
- cmd_buf = (uint32_t *)rga_service.cmd_buff + offset*28;\r
+ cmd_buf = (uint32_t *)rga_service.cmd_buff + offset*32;\r
reg_p = (uint32_t *)reg->cmd_reg;\r
\r
- for(i=0; i<28; i++)\r
+ for(i=0; i<32; i++)\r
{\r
cmd_buf[i] = reg_p[i];\r
}\r
printk("CMD_REG\n");\r
for (i=0; i<7; i++)\r
printk("%.8x %.8x %.8x %.8x\n", p[0 + i*4], p[1+i*4], p[2 + i*4], p[3 + i*4]);\r
+ printk("%.8x %.8x\n", p[0 + i*4], p[1+i*4]);\r
}\r
#endif\r
\r
for (i=0; i<7; i++)\r
printk("%.8x %.8x %.8x %.8x\n", rga_read(0x100 + i*16 + 0),\r
rga_read(0x100 + i*16 + 4), rga_read(0x100 + i*16 + 8), rga_read(0x100 + i*16 + 12));\r
+ printk("%.8x %.8x\n", rga_read(0x100 + i*16 + 0), rga_read(0x100 + i*16 + 4));\r
}\r
#endif\r
}\r
\r
}\r
\r
-\r
static int rga_convert_dma_buf(struct rga_req *req)\r
{\r
struct ion_handle *hdl;\r
ion_phys_addr_t phy_addr;\r
size_t len;\r
+ int ret;\r
+\r
+ req->sg_src = NULL;\r
+ req->sg_dst = NULL;\r
\r
if(req->src.yrgb_addr) {\r
hdl = ion_import_dma_buf(drvdata->ion_client, req->src.yrgb_addr);\r
- ion_phys(drvdata->ion_client, hdl, &phy_addr, &len);\r
- req->src.yrgb_addr = phy_addr;\r
- req->src.uv_addr = req->src.yrgb_addr + (req->src.vir_w * req->src.vir_h);\r
+ if (IS_ERR(hdl)) {\r
+ ret = PTR_ERR(hdl);\r
+ printk("RGA2 ERROR ion buf handle\n");\r
+ return ret;\r
+ }\r
+ if ((req->mmu_info.mmu_flag >> 8) & 1) {\r
+ req->sg_src = ion_sg_table(drvdata->ion_client, hdl);\r
+ req->src.yrgb_addr = req->src.uv_addr;\r
+ req->src.uv_addr = req->src.yrgb_addr + (req->src.vir_w * req->src.vir_h);\r
+ req->src.v_addr = req->src.uv_addr + (req->src.vir_w * req->src.vir_h)/4;\r
+ }\r
+ else {\r
+ ion_phys(drvdata->ion_client, hdl, &phy_addr, &len);\r
+ req->src.yrgb_addr = phy_addr;\r
+ req->src.uv_addr = req->src.yrgb_addr + (req->src.vir_w * req->src.vir_h);\r
+ req->src.v_addr = req->src.uv_addr + (req->src.vir_w * req->src.vir_h)/4;\r
+ }\r
ion_free(drvdata->ion_client, hdl);\r
}\r
else {\r
req->src.yrgb_addr = req->src.uv_addr;\r
req->src.uv_addr = req->src.yrgb_addr + (req->src.vir_w * req->src.vir_h);\r
+ req->src.v_addr = req->src.uv_addr + (req->src.vir_w * req->src.vir_h)/4;\r
}\r
\r
if(req->dst.yrgb_addr) {\r
hdl = ion_import_dma_buf(drvdata->ion_client, req->dst.yrgb_addr);\r
- ion_phys(drvdata->ion_client, hdl, &phy_addr, &len);\r
- req->dst.yrgb_addr = phy_addr;\r
- req->dst.uv_addr = req->dst.yrgb_addr + (req->dst.vir_w * req->dst.vir_h);\r
+ if (IS_ERR(hdl)) {\r
+ ret = PTR_ERR(hdl);\r
+ printk("RGA2 ERROR ion buf handle\n");\r
+ return ret;\r
+ }\r
+ if ((req->mmu_info.mmu_flag >> 10) & 1) {\r
+ req->sg_dst = ion_sg_table(drvdata->ion_client, hdl);\r
+ req->dst.yrgb_addr = req->dst.uv_addr;\r
+ req->dst.uv_addr = req->dst.yrgb_addr + (req->dst.vir_w * req->dst.vir_h);\r
+ req->dst.v_addr = req->dst.uv_addr + (req->dst.vir_w * req->dst.vir_h)/4;\r
+ }\r
+ else {\r
+ ion_phys(drvdata->ion_client, hdl, &phy_addr, &len);\r
+ req->dst.yrgb_addr = phy_addr;\r
+ req->dst.uv_addr = req->dst.yrgb_addr + (req->dst.vir_w * req->dst.vir_h);\r
+ req->dst.v_addr = req->dst.uv_addr + (req->dst.vir_w * req->dst.vir_h)/4;\r
+ }\r
ion_free(drvdata->ion_client, hdl);\r
}\r
else {\r
req->dst.yrgb_addr = req->dst.uv_addr;\r
- req->dst.uv_addr = req->dst.yrgb_addr + (req->src.vir_w * req->src.vir_h);\r
+ req->dst.uv_addr = req->dst.yrgb_addr + (req->dst.vir_w * req->dst.vir_h);\r
+ req->dst.v_addr = req->dst.uv_addr + (req->dst.vir_w * req->dst.vir_h)/4;\r
}\r
\r
return 0;\r
}\r
\r
+\r
static int rga_blit(rga_session *session, struct rga_req *req)\r
{\r
int ret = -1;\r
daw = req->dst.act_w;\r
dah = req->dst.act_h;\r
\r
+ #if RGA_TEST\r
+ print_info(req);\r
+ #endif\r
+\r
if(rga_convert_dma_buf(req)) {\r
printk("RGA : DMA buf copy error\n");\r
return -EFAULT;\r
}\r
\r
- #if RGA_TEST\r
- print_info(req);\r
- #endif\r
-\r
do {\r
if((req->render_mode == bitblt_mode) && (((saw>>1) >= daw) || ((sah>>1) >= dah))) {\r
/* generate 2 cmd for pre scale */\r
\r
\r
long rga_ioctl_kernel(struct rga_req *req)\r
+{\r
+ int ret = 0;\r
+ if (!rga_ioctl_kernel_p) {\r
+ printk("rga_ioctl_kernel_p is NULL\n");\r
+ return -1;\r
+ }\r
+ else {\r
+ ret = (*rga_ioctl_kernel_p)(req);\r
+ return ret;\r
+ }\r
+}\r
+\r
+\r
+long rga_ioctl_kernel_imp(struct rga_req *req)\r
{\r
int ret = 0;\r
rga_session *session;\r
return -EINVAL;\r
}\r
\r
- switch (RGA_BLIT_SYNC) {\r
- case RGA_BLIT_SYNC:\r
- ret = rga_blit_sync(session, req);\r
- break;\r
- case RGA_BLIT_ASYNC:\r
- break;\r
- case RGA_FLUSH:\r
- break;\r
- case RGA_GET_RESULT:\r
- break;\r
- case RGA_GET_VERSION:\r
- //ret = 0;\r
- break;\r
- default:\r
- ERR("unknown ioctl cmd!\n");\r
- ret = -EINVAL;\r
- break;\r
- }\r
+ ret = rga_blit_sync(session, req);\r
\r
mutex_unlock(&rga_service.mutex);\r
\r
\r
#if defined(CONFIG_OF)\r
static const struct of_device_id rockchip_rga_dt_ids[] = {\r
- { .compatible = "rockchip,rga", },\r
+ { .compatible = "rockchip,rga_drv", },\r
{},\r
};\r
#endif\r
rga_service.last_prc_src_format = 1; /* default is yuv first*/\r
rga_service.enable = false;\r
\r
+ rga_ioctl_kernel_p = rga_ioctl_kernel_imp;\r
+\r
data = devm_kzalloc(&pdev->dev, sizeof(struct rga_drvdata), GFP_KERNEL);\r
if(! data) {\r
ERR("failed to allocate driver data.\n");\r
return -1;\r
}\r
\r
- /* malloc 8 M buf */\r
- for(i=0; i<2048; i++)\r
+ /* malloc 4 M buf */\r
+ for(i=0; i<1024; i++)\r
{\r
buf_p = (uint32_t *)__get_free_page(GFP_KERNEL|__GFP_ZERO);\r
if(buf_p == NULL)\r
\r
rga_power_off();\r
\r
- for(i=0; i<2048; i++)\r
+ for(i=0; i<1024; i++)\r
{\r
if((uint32_t *)rga_service.pre_scale_buf[i] != NULL)\r
{\r
return status;\r
}\r
\r
+static int rga_MapION(struct sg_table *sg,\r
+ uint32_t *Memory,\r
+ int32_t pageCount)\r
+{\r
+ uint32_t i;\r
+ uint32_t status;\r
+ uint32_t Address;\r
+ uint32_t mapped_size = 0;\r
+ uint32_t len;\r
+ struct scatterlist *sgl = sg->sgl;\r
+ uint32_t sg_num = 0;\r
+\r
+ status = 0;\r
+ Address = 0;\r
+ do {\r
+ len = sg_dma_len(sgl) >> PAGE_SHIFT;\r
+ Address = sg_phys(sgl);\r
+\r
+ for(i=0; i<len; i++) {\r
+ Memory[mapped_size + i] = Address + (i << PAGE_SHIFT);\r
+ }\r
+\r
+ mapped_size += len;\r
+ sg_num += 1;\r
+ }\r
+ while((sgl = sg_next(sgl)) && (mapped_size < pageCount) && (sg_num < sg->nents));\r
+\r
+ return 0;\r
+}\r
+\r
+\r
static int rga_mmu_info_BitBlt_mode(struct rga_reg *reg, struct rga_req *req)\r
{\r
int SrcMemSize, DstMemSize;\r
\r
MMU_Base = NULL;\r
\r
+ SrcMemSize = 0;\r
+ DstMemSize = 0;\r
+\r
do\r
{\r
/* cal src buf mmu info */\r
+\r
SrcMemSize = rga_buf_size_cal(req->src.yrgb_addr, req->src.uv_addr, req->src.v_addr,\r
req->src.format, req->src.vir_w, req->src.act_h + req->src.y_offset,\r
&SrcStart);\r
return -EINVAL;\r
}\r
\r
+\r
/* cal dst buf mmu info */\r
+\r
DstMemSize = rga_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,\r
req->dst.format, req->dst.vir_w, req->dst.vir_h,\r
&DstStart);\r
return -EINVAL;\r
}\r
\r
+\r
/* Cal out the needed mem size */\r
AllSize = SrcMemSize + DstMemSize;\r
\r
break;\r
}\r
\r
- if(req->src.yrgb_addr < KERNEL_SPACE_VALID)\r
+ if((req->mmu_info.mmu_flag >> 8) & 1)\r
{\r
- ret = rga_MapUserMemory(&pages[0], &MMU_Base[0], SrcStart, SrcMemSize);\r
- if (ret < 0) {\r
- pr_err("rga map src memory failed\n");\r
- status = ret;\r
- break;\r
+ if (req->sg_src) {\r
+ ret = rga_MapION(req->sg_src, &MMU_Base[0], SrcMemSize);\r
+ }\r
+ else {\r
+ ret = rga_MapUserMemory(&pages[0], &MMU_Base[0], SrcStart, SrcMemSize);\r
+ if (ret < 0) {\r
+ pr_err("rga map src memory failed\n");\r
+ status = ret;\r
+ break;\r
+ }\r
}\r
}\r
else\r
/* MMU table copy from pre scale table */\r
\r
for(i=0; i<SrcMemSize; i++)\r
- {\r
MMU_p[i] = rga_service.pre_scale_buf[i];\r
- }\r
+\r
}\r
- else\r
- {\r
+ else {\r
for(i=0; i<SrcMemSize; i++)\r
- {\r
- MMU_p[i] = (uint32_t)virt_to_phys((uint32_t *)((SrcStart + i) << PAGE_SHIFT));\r
- }\r
+ MMU_p[i] = (uint32_t)((SrcStart + i) << PAGE_SHIFT);\r
}\r
}\r
\r
- if (req->dst.yrgb_addr < KERNEL_SPACE_VALID)\r
- {\r
- #if 0\r
- ktime_t start, end;\r
- start = ktime_get();\r
- #endif\r
+ if ((req->mmu_info.mmu_flag >> 10) & 1) {\r
ret = rga_MapUserMemory(&pages[SrcMemSize], &MMU_Base[SrcMemSize], DstStart, DstMemSize);\r
if (ret < 0) {\r
pr_err("rga map dst memory failed\n");\r
status = ret;\r
break;\r
}\r
-\r
- #if 0\r
- end = ktime_get();\r
- end = ktime_sub(end, start);\r
- printk("dst mmu map time = %d\n", (int)ktime_to_us(end));\r
- #endif\r
}\r
- else\r
- {\r
+ else {\r
MMU_p = MMU_Base + SrcMemSize;\r
\r
for(i=0; i<DstMemSize; i++)\r
- {\r
- MMU_p[i] = (uint32_t)virt_to_phys((uint32_t *)((DstStart + i) << PAGE_SHIFT));\r
- }\r
+ MMU_p[i] = (uint32_t)((DstStart + i) << PAGE_SHIFT);\r
}\r
\r
MMU_Base[AllSize] = MMU_Base[AllSize - 1];\r
s32 RGA_set_dst(u8 *base, const struct rga_req *msg)\r
{\r
u32 *bRGA_DST_MST;\r
+ u32 *bRGA_DST_UV_MST;\r
u32 *bRGA_DST_VIR_INFO;\r
u32 *bRGA_DST_CTR_INFO;\r
u32 *bRGA_PRESCL_CB_MST;\r
u32 *bRGA_PRESCL_CR_MST;\r
+ u32 *bRGA_YUV_OUT_CFG;\r
+\r
u32 reg = 0;\r
\r
u8 pw;\r
u16 stride, rop_mask_stride;\r
\r
bRGA_DST_MST = (u32 *)(base + RGA_DST_MST_OFFSET);\r
+ bRGA_DST_UV_MST = (u32 *)(base + RGA_DST_UV_MST_OFFSET);\r
bRGA_DST_VIR_INFO = (u32 *)(base + RGA_DST_VIR_INFO_OFFSET);\r
bRGA_DST_CTR_INFO = (u32 *)(base + RGA_DST_CTR_INFO_OFFSET);\r
bRGA_PRESCL_CB_MST = (u32 *)(base + RGA_PRESCL_CB_MST_OFFSET);\r
bRGA_PRESCL_CR_MST = (u32 *)(base + RGA_PRESCL_CR_MST_OFFSET);\r
+ bRGA_YUV_OUT_CFG = (u32 *)(base + RGA_YUV_OUT_CFG_OFFSET);\r
\r
pw = RGA_pixel_width_init(msg->dst.format);\r
\r
\r
*bRGA_DST_MST = (u32)msg->dst.yrgb_addr + (y_off * stride) + (x_off * pw);\r
\r
- if (msg->render_mode == pre_scaling_mode)\r
+ *bRGA_DST_UV_MST = 0;\r
+ *bRGA_YUV_OUT_CFG = 0;\r
+ switch(msg->dst.format)\r
{\r
- switch(msg->dst.format)\r
- {\r
- case RK_FORMAT_YCbCr_422_SP :\r
- *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw);\r
- break;\r
- case RK_FORMAT_YCbCr_422_P :\r
- *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw);\r
- *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off) * stride) + ((x_off>>1) * pw);\r
- break;\r
- case RK_FORMAT_YCbCr_420_SP :\r
- *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw);\r
- break;\r
- case RK_FORMAT_YCbCr_420_P :\r
- *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);\r
- *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);\r
- break;\r
- case RK_FORMAT_YCrCb_422_SP :\r
- *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw);\r
- break;\r
- case RK_FORMAT_YCrCb_422_P :\r
- *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw);\r
- *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off) * stride) + ((x_off>>1) * pw);\r
- break;\r
- case RK_FORMAT_YCrCb_420_SP :\r
- *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw);\r
- break;\r
- case RK_FORMAT_YCrCb_420_P :\r
- *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);\r
- *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);\r
- break;\r
- }\r
+ case RK_FORMAT_YCbCr_422_SP :\r
+ *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw);\r
+ *bRGA_DST_UV_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off));\r
+ *bRGA_YUV_OUT_CFG |= (1 << 3) | 1 | ((msg->yuv2rgb_mode >> 4) & 2);\r
+ break;\r
+ case RK_FORMAT_YCbCr_422_P :\r
+ *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw);\r
+ *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off) * stride) + ((x_off>>1) * pw);\r
+ break;\r
+ case RK_FORMAT_YCbCr_420_SP :\r
+ *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw);\r
+ *bRGA_DST_UV_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off));\r
+ *bRGA_YUV_OUT_CFG |= (1 << 3)|(1 << 1) | 1 | ((msg->yuv2rgb_mode >> 4) & 2);\r
+ break;\r
+ case RK_FORMAT_YCbCr_420_P :\r
+ *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);\r
+ *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);\r
+ break;\r
+ case RK_FORMAT_YCrCb_422_SP :\r
+ *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw);\r
+ *bRGA_DST_UV_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off));\r
+ *bRGA_YUV_OUT_CFG |= (0 << 3)|(0 << 1) | 1 | ((msg->yuv2rgb_mode >> 4) & 2);\r
+ break;\r
+ case RK_FORMAT_YCrCb_422_P :\r
+ *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw);\r
+ *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off) * stride) + ((x_off>>1) * pw);\r
+ break;\r
+ case RK_FORMAT_YCrCb_420_SP :\r
+ *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw);\r
+ *bRGA_DST_UV_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off));\r
+ *bRGA_YUV_OUT_CFG |= (0 << 3)|(1 << 1) | 1 | ((msg->yuv2rgb_mode >> 4) & 2);\r
+ break;\r
+ case RK_FORMAT_YCrCb_420_P :\r
+ *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);\r
+ *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);\r
+ break;\r
}\r
\r
rop_mask_stride = (((msg->src.vir_w + 7)>>3) + 3) & (~3);//not dst_vir.w,hxx,2011.7.21\r
*bRGA_DST_VIR_INFO = reg;\r
*bRGA_DST_CTR_INFO = (msg->dst.act_w - 1) | ((msg->dst.act_h - 1) << 16);\r
\r
+ if (msg->render_mode == pre_scaling_mode) {\r
+ *bRGA_YUV_OUT_CFG &= 0xfffffffe;\r
+ }\r
+\r
return 0;\r
}\r
\r
#define rRGA_DST_VIR_INFO (*(volatile uint32_t *)(RGA_BASE + RGA_DST_VIR_INFO))\r
\r
#define rRGA_DST_CTR_INFO (*(volatile uint32_t *)(RGA_BASE + RGA_DST_CTR_INFO))\r
-#define rRGA_LINE_DRAW_XY_INFO (*(volatile uint32_t *)(RGA_BASE + RGA_LINE_DRAW_XY_INFO)) //repeat \r
+#define rRGA_LINE_DRAW_XY_INFO (*(volatile uint32_t *)(RGA_BASE + RGA_LINE_DRAW_XY_INFO)) //repeat\r
\r
//Alpha/ROP Registers\r
#define rRGA_ALPHA_CON (*(volatile uint32_t *)(RGA_BASE + RGA_ALPHA_CON))\r
#define s_RGA_LINE_DRAW_LAST_POINT(x) ( ((x)&0x1)<<30)\r
#define s_RGA_LINE_DRAW_ANTI_ALISING(x) ( ((x)&0x1)<<31)\r
\r
- \r
+\r
/* RGA_ALPHA_CON */\r
#define m_RGA_ALPHA_CON_ENABLE ( 0x1<<0 )\r
#define m_RGA_ALPHA_CON_A_OR_R_SEL ( 0x1<<1 )\r
#define RGA_DST_VIR_INFO_OFFSET 0x50\r
\r
#define RGA_DST_CTR_INFO_OFFSET 0x54\r
-#define RGA_LINE_DRAW_XY_INFO_OFFSET 0x54 //repeat \r
+#define RGA_LINE_DRAW_XY_INFO_OFFSET 0x54 //repeat\r
\r
#define RGA_ALPHA_CON_OFFSET 0x58\r
#define RGA_FADING_CON_OFFSET 0x5c\r
#define RGA_DST_VIR_INFO_OFFSET (RGA_DST_VIR_INFO-0x100)\r
\r
#define RGA_DST_CTR_INFO_OFFSET (RGA_DST_CTR_INFO-0x100)\r
-#define RGA_LINE_DRAW_XY_INFO_OFFSET (RGA_LINE_DRAW_XY_INFO-0x100) //repeat \r
+#define RGA_LINE_DRAW_XY_INFO_OFFSET (RGA_LINE_DRAW_XY_INFO-0x100) //repeat\r
\r
#define RGA_ALPHA_CON_OFFSET (RGA_ALPHA_CON-0x100)\r
\r
#define RGA_PRESCL_CR_MST_OFFSET (RGA_PRESCL_CR_MST-0x100) //repeat\r
\r
#define RGA_FADING_CON_OFFSET (RGA_FADING_CON-0x100)\r
-#define RGA_MMU_TLB_OFFSET (RGA_MMU_TBL-0x100)\r
+#define RGA_MMU_TLB_OFFSET (RGA_MMU_TBL-0x100)\r
+\r
+#define RGA_YUV_OUT_CFG_OFFSET (RGA_YUV_OUT_CFG-0x100)\r
+#define RGA_DST_UV_MST_OFFSET (RGA_DST_UV_MST-0x100)\r
+\r
\r
\r
void matrix_cal(const struct rga_req *msg, TILE_INFO *tile);\r
#ifndef __RGA_ROP_H__\r
#define __RGA_ROP_H__\r
\r
-#include "rga_type.h"\r
-\r
-UWORD32 ROP3_code[256] = \r
+unsigned int ROP3_code[256] =\r
{\r
0x00000007, 0x00000451, 0x00006051, 0x00800051, 0x00007041, 0x00800041, 0x00804830, 0x000004f0,//0\r
0x00800765, 0x000004b0, 0x00000065, 0x000004f4, 0x00000075, 0x000004e6, 0x00804850, 0x00800005,\r
\r
- 0x00006850, 0x00800050, 0x00805028, 0x00000568, 0x00804031, 0x00000471, 0x002b6071, 0x018037aa,//1 \r
+ 0x00006850, 0x00800050, 0x00805028, 0x00000568, 0x00804031, 0x00000471, 0x002b6071, 0x018037aa,//1\r
0x008007aa, 0x00036071, 0x00002c6a, 0x00803631, 0x00002d68, 0x00802721, 0x008002d0, 0x000006d0,\r
\r
0x0080066e, 0x00000528, 0x00000066, 0x0000056c, 0x018007aa, 0x0002e06a, 0x00003471, 0x00834031,//2\r
\r
0x00006870, 0x008037a2, 0x00003431, 0x00000745, 0x00002521, 0x00000655, 0x0000346e, 0x00800062,\r
0x008002f0, 0x000236d0, 0x000026d4, 0x00807028, 0x000036c6, 0x00806031, 0x008005aa, 0x00000671,//7\r
- \r
- 0x00800671, 0x000005aa, 0x00006031, 0x008036c6, 0x00007028, 0x00802e55, 0x008236d0, 0x000002f0, \r
+\r
+ 0x00800671, 0x000005aa, 0x00006031, 0x008036c6, 0x00007028, 0x00802e55, 0x008236d0, 0x000002f0,\r
0x00000070, 0x0080346e, 0x00800655, 0x00802521, 0x00800745, 0x00803431, 0x000037a2, 0x00806870,//8\r
\r
0x00006830, 0x0080364e, 0x00822f48, 0x00000361, 0x0082b651, 0x00000271, 0x00800231, 0x002b4051,\r
#define RGA2_MODE_CTRL 0x100\r
#define RGA_BLIT_COMPLETE_EVENT 1\r
\r
-long rga_ioctl_kernel(struct rga_req *req);\r
-\r
-\r
#endif /*_RK29_IPP_DRIVER_H_*/\r
\r
int rga2_flag = 0;\r
\r
+extern long (*rga_ioctl_kernel_p)(struct rga_req *);\r
+\r
rga2_session rga2_session_global;\r
\r
struct rga2_drvdata_t {\r
};\r
\r
static const struct of_device_id rockchip_rga_dt_ids[] = {\r
- { .compatible = "rockchip,rga2", },\r
+ { .compatible = "rockchip,rga2_drv", },\r
{},\r
};\r
\r
rga2_service.last_prc_src_format = 1; /* default is yuv first*/\r
rga2_service.enable = false;\r
\r
+ rga_ioctl_kernel_p = rga2_ioctl_kernel;\r
+\r
data = devm_kzalloc(&pdev->dev, sizeof(struct rga2_drvdata_t), GFP_KERNEL);\r
if(NULL == data)\r
{\r
.remove = rga2_drv_remove,\r
.driver = {\r
.owner = THIS_MODULE,\r
- .name = "rga",\r
+ .name = "rga2",\r
.of_match_table = of_match_ptr(rockchip_rga_dt_ids),\r
},\r
};\r
#include <linux/wakelock.h>\r
\r
#include "rga2_reg_info.h"\r
-#include "rga2_rop.h"\r
+#include "../rga/rga_type.h"\r
+//#include "../rga/rga_rop.h"\r
#include "rga2.h"\r
\r
+extern unsigned int ROP3_code[256];\r
\r
void\r
RGA2_reg_get_param(unsigned char *base, struct rga2_req *msg)\r
\r
#include "rga2_type.h"\r
\r
-extern UWORD32 ROP3_code[256];\r
-\r
-#if 0\r
-extern UWORD32 ROP3_code[256] =\r
+UWORD32 ROP3_code[256] =\r
{\r
0x00000007, 0x00000451, 0x00006051, 0x00800051, 0x00007041, 0x00800041, 0x00804830, 0x000004f0,//0\r
0x00800765, 0x000004b0, 0x00000065, 0x000004f4, 0x00000075, 0x000004e6, 0x00804850, 0x00800005,\r
0x00800001, 0x00004850, 0x008004e6, 0x0000004e, 0x008004f4, 0x0000004c, 0x008004b0, 0x00004870,\r
0x008004f0, 0x00004830, 0x00000048, 0x0080044e, 0x00000051, 0x008004d4, 0x00800451, 0x00800007,//f\r
};\r
-#endif\r
\r
#endif\r
projects / firefly-linux-kernel-4.4.55.git / commitdiff