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81ea655)
Change-Id: I031fb437a84b19bb7cc389acb2404777f732cf6c
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
compatible = "rockchip,rk3368-isp", "rockchip,isp";
reg = <0x0 0xff910000 0x0 0x10000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
compatible = "rockchip,rk3368-isp", "rockchip,isp";
reg = <0x0 0xff910000 0x0 0x10000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- /*power-domains = <&power PD_VIO>;*/
+ power-domains = <&power RK3368_PD_VIO>;
clocks =
<&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
<&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
clocks =
<&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
<&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
assigned-clocks = <&cru ACLK_VOP>;
assigned-clock-rates = <400000000>;
clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
assigned-clocks = <&cru ACLK_VOP>;
assigned-clock-rates = <400000000>;
- /*power-domains = <&power PD_VIO>;*/
+ power-domains = <&power RK3368_PD_VIO>;
resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
reset-names = "axi", "ahb", "dclk";
};
resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
reset-names = "axi", "ahb", "dclk";
};
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
- /*power-domains = <&power PD_VIO>;*/
+ power-domains = <&power RK3368_PD_VIO>;
reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
clock-names = "pclk_lvds", "pclk_lvds_ctl";
reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
clock-names = "pclk_lvds", "pclk_lvds_ctl";
- /*power-domains = <&power PD_VIO>;*/
+ power-domains = <&power RK3368_PD_VIO>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
- /*power-domains = <&power PD_VIO>;*/
+ power-domains = <&power RK3368_PD_VIO>;
resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
reset-names = "edp_24m", "edp_apb";
status = "disabled";
resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
reset-names = "edp_24m", "edp_apb";
status = "disabled";
<&cru SCLK_HDMI_HDCP>,
<&cru SCLK_HDMI_CEC>;
clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
<&cru SCLK_HDMI_HDCP>,
<&cru SCLK_HDMI_CEC>;
clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
- /*power-domains = <&power PD_VIO>;*/
+ power-domains = <&power RK3368_PD_VIO>;
resets = <&cru SRST_HDMI>;
reset-names = "hdmi";
pinctrl-names = "default", "gpio";
resets = <&cru SRST_HDMI>;
reset-names = "hdmi";
pinctrl-names = "default", "gpio";
reg = <0x0 0xff730000 0x0 0x1000>;
power: power-controller {
reg = <0x0 0xff730000 0x0 0x1000>;
power: power-controller {
compatible = "rockchip,rk3368-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
compatible = "rockchip,rk3368-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
"aclk_gpu_cfg";
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "rogue-g6110-irq";
"aclk_gpu_cfg";
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "rogue-g6110-irq";
+ power-domains = <&power RK3368_PD_GPU_1>;
operating-points-v2 = <&gpu_opp_table>;
};
operating-points-v2 = <&gpu_opp_table>;
};