{I2C_MASTER_BASE, I2CM_SCDC_UPDATE1},
};
-static int rockchip_hdmiv2_reg_show(struct seq_file *s, void *v)
+static int hdmi_regs_ctrl_show(struct seq_file *s, void *v)
{
- int i = 0, j = 0;
- u32 val = 0;
+ u32 i = 0, j = 0, val = 0;
seq_puts(s, "\n>>>hdmi_ctl reg ");
for (i = 0; i < 16; i++)
}
seq_puts(s, "\n-----------------------------------------------------------------\n");
- /*rockchip_hdmiv2_dump_phy_regs(hdmi_dev);*/
return 0;
}
-static ssize_t rockchip_hdmiv2_reg_write(struct file *file,
- const char __user *buf,
- size_t count, loff_t *ppos)
+static ssize_t hdmi_regs_ctrl_write(struct file *file,
+ const char __user *buf,
+ size_t count, loff_t *ppos)
{
- u32 reg;
- u32 val;
+ u32 reg, val;
char kbuf[25];
if (copy_from_user(kbuf, buf, count))
return count;
}
-static int rockchip_hdmiv2_reg_open(struct inode *inode, struct file *file)
+static int hdmi_regs_phy_show(struct seq_file *s, void *v)
{
- struct hdmi_dev *hdmi_dev = inode->i_private;
+ u32 i;
- return single_open(file, rockchip_hdmiv2_reg_show, hdmi_dev);
+ seq_puts(s, "\n>>>hdmi_phy reg ");
+ for (i = 0; i < 0x28; i++)
+ seq_printf(s, "regs %02x val %04x\n",
+ i, rockchip_hdmiv2_read_phy(hdmi_dev, i));
+ return 0;
}
-static const struct file_operations rockchip_hdmiv2_reg_fops = {
- .owner = THIS_MODULE,
- .open = rockchip_hdmiv2_reg_open,
- .read = seq_read,
- .write = rockchip_hdmiv2_reg_write,
- .llseek = seq_lseek,
- .release = single_release,
-};
+static ssize_t hdmi_regs_phy_write(struct file *file,
+ const char __user *buf,
+ size_t count, loff_t *ppos)
+{
+ u32 reg, val;
+ char kbuf[25];
+
+ if (copy_from_user(kbuf, buf, count))
+ return -EFAULT;
+ if (sscanf(kbuf, "%x%x", ®, &val) == -1)
+ return -EFAULT;
+ dev_info(hdmi_dev->hdmi->dev,
+ "/**********hdmi reg phy config******/");
+ dev_info(hdmi_dev->hdmi->dev, "\n reg=%x val=%x\n", reg, val);
+ rockchip_hdmiv2_write_phy(hdmi_dev, reg, val);
+ return count;
+}
+
+#define HDMI_DEBUG_ENTRY(name) \
+static int hdmi_##name##_open(struct inode *inode, struct file *file) \
+{ \
+ return single_open(file, hdmi_##name##_show, inode->i_private); \
+} \
+\
+static const struct file_operations hdmi_##name##_fops = { \
+ .owner = THIS_MODULE, \
+ .open = hdmi_##name##_open, \
+ .read = seq_read, \
+ .write = hdmi_##name##_write, \
+ .llseek = seq_lseek, \
+ .release = single_release, \
+}
+
+HDMI_DEBUG_ENTRY(regs_phy);
+HDMI_DEBUG_ENTRY(regs_ctrl);
#endif
#ifdef CONFIG_HAS_EARLYSUSPEND
if (IS_ERR(hdmi_dev->debugfs_dir))
dev_err(hdmi_dev->hdmi->dev,
"failed to create debugfs dir for rockchip hdmiv2!\n");
- else
- debugfs_create_file("hdmi", S_IRUSR,
+ else {
+ debugfs_create_file("regs_ctrl", S_IRUSR,
hdmi_dev->debugfs_dir,
- hdmi_dev, &rockchip_hdmiv2_reg_fops);
+ hdmi_dev, &hdmi_regs_ctrl_fops);
+ debugfs_create_file("regs_phy", S_IRUSR,
+ hdmi_dev->debugfs_dir,
+ hdmi_dev, &hdmi_regs_phy_fops);
+ }
#endif
rk_display_device_enable(hdmi_dev->hdmi->ddev);
hdmi_writel(hdmi_dev, MC_CLKDIS, 0x7f);
}
-static int rockchip_hdmiv2_write_phy(struct hdmi_dev *hdmi_dev,
- int reg_addr, int val)
+int rockchip_hdmiv2_write_phy(struct hdmi_dev *hdmi_dev,
+ int reg_addr, int val)
{
int trytime = 2, i = 0, op_status = 0;
return -1;
}
-static int __maybe_unused rockchip_hdmiv2_read_phy(struct hdmi_dev *hdmi_dev,
- int reg_addr)
+int rockchip_hdmiv2_read_phy(struct hdmi_dev *hdmi_dev,
+ int reg_addr)
{
int trytime = 2, i = 0, op_status = 0;
int val = 0;
phy_mpll->gmp_cntrl));
}
rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_TERM_RESIS,
- v_TX_TERM(R50_OHMS));
+ v_TX_TERM(R50_OHMS));
rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_CLKSYMCTRL,
v_OVERRIDE(1) | v_SLOPEBOOST(0) |
v_TX_SYMON(1) | v_TX_TRAON(0) |