i2c: rockchip: add i2c supported for rk3228

Change-Id: I3836b589f3ba456869f20a0ad97e6cde031debfd
Signed-off-by: David Wu <wdc@rock-chips.com>

diff --git a/arch/arm/boot/dts/rk3228.dtsi b/arch/arm/boot/dts/rk3228.dtsi
index 0f9dd316578ace805bdb5322af8db9fe11643ad2..cdee2e5221e5f01d23c6d78fb5003a090d814505 100644 (file)
--- a/arch/arm/boot/dts/rk3228.dtsi
+++ b/arch/arm/boot/dts/rk3228.dtsi
@@ -13,6 +13,10 @@
 
        aliases {
                serial2 = &uart_dbg;
+               i2c0 = &i2c0;
+               i2c1 = &i2c1;
+               i2c2 = &i2c2;
+               i2c3 = &i2c3;
        };
 
        cpus {
@@ -199,6 +203,74 @@
                        <&clk_gates1 3>;/*clk_jtag*/
        };
 
+       i2c0: i2c@11050000 {
+               compatible = "rockchip,rk30-i2c";
+               reg = <0x11050000 0x1000>;
+               interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               pinctrl-names = "default", "gpio", "sleep";
+               pinctrl-0 = <&i2c0_xfer>;
+               pinctrl-1 = <&i2c0_gpio>;
+               pinctrl-2 = <&i2c0_sleep>;
+               gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>,
+                       <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
+               clocks = <&clk_gates8 15>;
+               rockchip,check-idle = <1>;
+               status = "disabled";
+       };
+
+       i2c1: i2c@11060000 {
+               compatible = "rockchip,rk30-i2c";
+               reg = <0x11060000 0x1000>;
+               interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               pinctrl-names = "default", "gpio", "sleep";
+               pinctrl-0 = <&i2c1_xfer>;
+               pinctrl-1 = <&i2c1_gpio>;
+               pinctrl-2 = <&i2c1_sleep>;
+               gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>,
+                       <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
+               clocks = <&clk_gates9 0>;
+               rockchip,check-idle = <1>;
+               status = "disabled";
+       };
+
+       i2c2: i2c@11070000 {
+               compatible = "rockchip,rk30-i2c";
+               reg = <0x11070000 0x1000>;
+               interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               pinctrl-names = "default", "gpio", "sleep";
+               pinctrl-0 = <&i2c2_xfer>;
+               pinctrl-1 = <&i2c2_gpio>;
+               pinctrl-2 = <&i2c2_sleep>;
+               gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>,
+                       <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
+               clocks = <&clk_gates9 1>;
+               rockchip,check-idle = <1>;
+               status = "disabled";
+       };
+
+       i2c3: i2c@11080000 {
+               compatible = "rockchip,rk30-i2c";
+               reg = <0x11080000 0x1000>;
+               interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               pinctrl-names = "default", "gpio", "sleep";
+               pinctrl-0 = <&i2c3_xfer>;
+               pinctrl-1 = <&i2c3_gpio>;
+               pinctrl-2 = <&i2c3_sleep>;
+               gpios = <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>,
+                       <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>;
+               clocks = <&clk_gates9 2>;
+               rockchip,check-idle = <1>;
+               status = "disabled";
+       };
+
        amba {
                #address-cells = <1>;
                #size-cells = <1>;