drm/exynos/decon5433: fix timing registers writes

All timing registers should contain values decreased by one.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
index b25d764ae5e1cdf8e8a4e72fe7a5ec0a9b7d5fdd..83e09396bfb33f06d6c8bdc09724b2219ba07460 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -104,7 +104,7 @@ static void decon_setup_trigger(struct decon_context *ctx)
 static void decon_commit(struct exynos_drm_crtc *crtc)
 {
        struct decon_context *ctx = crtc->ctx;
-       struct drm_display_mode *mode = &crtc->base.mode;
+       struct drm_display_mode *m = &crtc->base.mode;
        u32 val;
 
        if (ctx->suspended)
@@ -122,29 +122,29 @@ static void decon_commit(struct exynos_drm_crtc *crtc)
                val |= VIDOUT_RGB_IF;
        writel(val, ctx->addr + DECON_VIDOUTCON0);
 
-       val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
-               VIDTCON2_HOZVAL(mode->hdisplay - 1);
+       val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
+               VIDTCON2_HOZVAL(m->hdisplay - 1);
        writel(val, ctx->addr + DECON_VIDTCON2);
 
        if (!ctx->i80_if) {
                val = VIDTCON00_VBPD_F(
-                               mode->crtc_vtotal - mode->crtc_vsync_end) |
+                               m->crtc_vtotal - m->crtc_vsync_end - 1) |
                        VIDTCON00_VFPD_F(
-                               mode->crtc_vsync_start - mode->crtc_vdisplay);
+                               m->crtc_vsync_start - m->crtc_vdisplay - 1);
                writel(val, ctx->addr + DECON_VIDTCON00);
 
                val = VIDTCON01_VSPW_F(
-                               mode->crtc_vsync_end - mode->crtc_vsync_start);
+                               m->crtc_vsync_end - m->crtc_vsync_start - 1);
                writel(val, ctx->addr + DECON_VIDTCON01);
 
                val = VIDTCON10_HBPD_F(
-                               mode->crtc_htotal - mode->crtc_hsync_end) |
+                               m->crtc_htotal - m->crtc_hsync_end - 1) |
                        VIDTCON10_HFPD_F(
-                               mode->crtc_hsync_start - mode->crtc_hdisplay);
+                               m->crtc_hsync_start - m->crtc_hdisplay - 1);
                writel(val, ctx->addr + DECON_VIDTCON10);
 
                val = VIDTCON11_HSPW_F(
-                               mode->crtc_hsync_end - mode->crtc_hsync_start);
+                               m->crtc_hsync_end - m->crtc_hsync_start - 1);
                writel(val, ctx->addr + DECON_VIDTCON11);
        }