--- /dev/null
+/*
+ * Copyright (C) 2014-2015 ROCKCHIP, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <dt-bindings/clock/rockchip,rk3228.h>
+
+/{
+ clocks {
+ compatible = "rockchip,rk-clocks";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x110e0000 0x1000>;
+
+ fixed_rate_cons {
+ compatible = "rockchip,rk-fixed-rate-cons";
+
+ xin24m: xin24m {
+ compatible = "rockchip,rk-fixed-clock";
+ clock-output-names = "xin24m";
+ clock-frequency = <24000000>;
+ #clock-cells = <0>;
+ };
+
+ xin12m: xin12m {
+ compatible = "rockchip,rk-fixed-clock";
+ clocks = <&xin24m>;
+ clock-output-names = "xin12m";
+ clock-frequency = <12000000>;
+ #clock-cells = <0>;
+ };
+
+ hdmiphy_out: hdmiphy_out {
+ compatible = "rockchip,rk-fixed-clock";
+ clock-output-names = "hdmiphy_out";
+ clock-frequency = <594000000>;
+ #clock-cells = <0>;
+ };
+
+ usbphy0_480m: usbphy0_480m {
+ compatible = "rockchip,rk-fixed-clock";
+ clock-output-names = "usbphy0_480m";
+ clock-frequency = <480000000>;
+ #clock-cells = <0>;
+ };
+
+ usbphy1_480m: usbphy1_480m {
+ compatible = "rockchip,rk-fixed-clock";
+ clock-output-names = "usbphy1_480m";
+ clock-frequency = <480000000>;
+ #clock-cells = <0>;
+ };
+
+ jtag_clkin: jtag_clkin {
+ compatible = "rockchip,rk-fixed-clock";
+ clock-output-names = "jtag_clkin";
+ clock-frequency = <0>;
+ #clock-cells = <0>;
+ };
+
+ dummy: dummy {
+ compatible = "rockchip,rk-fixed-clock";
+ clock-output-names = "dummy";
+ clock-frequency = <0>;
+ #clock-cells = <0>;
+ };
+
+ gmac_clkin: gmac_clkin {
+ compatible = "rockchip,rk-fixed-clock";
+ clock-output-names = "gmac_clkin";
+ clock-frequency = <0>;
+ #clock-cells = <0>;
+ };
+
+ phy_50m_out: phy_50m_out {
+ compatible = "rockchip,rk-fixed-clock";
+ clock-output-names = "phy_50m_out";
+ clock-frequency = <0>;
+ #clock-cells = <0>;
+ };
+
+ phy_rx_out: phy_rx_out {
+ compatible = "rockchip,rk-fixed-clock";
+ clock-output-names = "phy_rx_out";
+ clock-frequency = <0>;
+ #clock-cells = <0>;
+ };
+
+ phy_tx_out: phy_tx_out {
+ compatible = "rockchip,rk-fixed-clock";
+ clock-output-names = "phy_tx_out";
+ clock-frequency = <0>;
+ #clock-cells = <0>;
+ };
+
+ clkin_hsadc_tsp: clkin_hsadc_tsp {
+ compatible = "rockchip,rk-fixed-clock";
+ clock-output-names = "clkin_hsadc_tsp";
+ clock-frequency = <0>;
+ #clock-cells = <0>;
+ };
+
+ i2s_clkin: i2s_clkin {
+ compatible = "rockchip,rk-fixed-clock";
+ clock-output-names = "i2s_clkin";
+ clock-frequency = <0>;
+ #clock-cells = <0>;
+ };
+ };
+
+ fixed_factor_cons {
+ compatible = "rockchip,rk-fixed-factor-cons";
+
+ hclk_rkvdec: hclk_rkvdec {
+ compatible = "rockchip,rk-fixed-factor-clock";
+ clocks = <&aclk_rkvdec>;
+ clock-output-names = "hclk_rkvdec";
+ clock-div = <4>;
+ clock-mult = <1>;
+ #clock-cells = <0>;
+ };
+
+ hclk_vpu: hclk_vpu {
+ compatible = "rockchip,rk-fixed-factor-clock";
+ clocks = <&aclk_vpu>;
+ clock-output-names = "hclk_vpu";
+ clock-div = <4>;
+ clock-mult = <1>;
+ #clock-cells = <0>;
+ };
+
+ xin32k_out: xin32k_out {
+ compatible = "rockchip,rk-fixed-clock";
+ clocks = <&clk_hdmi_cec>;
+ clock-output-names = "xin32k_out";
+ clock-div = <1>;
+ clock-mult = <1>;
+ #clock-cells = <0>;
+ };
+
+ };
+
+ clock_regs {
+ compatible = "rockchip,rk-clock-regs";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0000 0x1000>;
+ ranges;
+
+ /* PLL control regs */
+ pll_cons {
+ compatible = "rockchip,rk-pll-cons";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clk_apll: pll-clk@0000 {
+ compatible = "rockchip,rk3188-pll-clk";
+ reg = <0x0000 0x10>;
+ mode-reg = <0x0040 0>;
+ status-reg = <0x04 10>;
+ clocks = <&xin24m>;
+ clock-output-names = "clk_apll";
+ rockchip,pll-type = <CLK_PLL_3036_APLL>;
+ #clock-cells = <0>;
+ };
+
+ clk_dpll: pll-clk@000c {
+ compatible = "rockchip,rk3188-pll-clk";
+ reg = <0x000c 0x10>;
+ mode-reg = <0x0040 4>;
+ status-reg = <0x10 10>;
+ clocks = <&xin24m>;
+ clock-output-names = "clk_dpll";
+ rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
+ #clock-cells = <0>;
+ };
+
+
+ clk_cpll: pll-clk@0018 {
+ compatible = "rockchip,rk3188-pll-clk";
+ reg = <0x0018 0x10>;
+ mode-reg = <0x0040 8>;
+ status-reg = <0x1c 10>;
+ clocks = <&xin24m>;
+ clock-output-names = "clk_cpll";
+ rockchip,pll-type = <CLK_PLL_312XPLUS>;
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ clk_gpll: pll-clk@0024 {
+ compatible = "rockchip,rk3188-pll-clk";
+ reg = <0x0024 0x10>;
+ mode-reg = <0x0040 12>;
+ status-reg = <0x28 10>;
+ clocks = <&xin24m>;
+ clock-output-names = "clk_gpll";
+ rockchip,pll-type = <CLK_PLL_312XPLUS>;
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+ };
+
+ /* Select control regs */
+ clk_sel_cons {
+ compatible = "rockchip,rk-sel-cons";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clk_sel_con0: sel-con@0044 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0044 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_core_div: clk_core_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 5>;
+ clocks = <&clk_core>;
+ clock-output-names = "clk_core";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
+ rockchip,flags = <(CLK_GET_RATE_NOCACHE |
+ CLK_SET_RATE_NO_REPARENT)>;
+ };
+
+ /* 5 reserved */
+
+ clk_core: clk_core_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <6 2>;
+ clocks = <&clk_apll>, <&clk_gpll>, <&clk_dpll>;
+ clock-output-names = "clk_core";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ aclk_bus: aclk_bus_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 5>;
+ clocks = <&aclk_bus_mux>;
+ clock-output-names = "aclk_bus";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ aclk_bus_mux: aclk_bus_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <13 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>;
+ clock-output-names = "aclk_bus";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ /* 15 reserved */
+
+ };
+
+ clk_sel_con1: sel-con@0048 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0048 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pclk_dbg: pclk_dbg_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 4>;
+ clocks = <&clk_core>;
+ clock-output-names = "pclk_dbg";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
+ };
+
+ aclk_core: aclk_core_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <4 3>;
+ clocks = <&clk_core>;
+ clock-output-names = "aclk_core";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
+ };
+
+ /* 7 reserved */
+
+ hclk_bus: hclk_bus_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 2>;
+ clocks = <&aclk_bus>;
+ clock-output-names = "hclk_bus";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ /* 11:10 reserved */
+
+ pclk_bus: pclk_bus_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <12 3>;
+ clocks = <&aclk_bus>;
+ clock-output-names = "pclk_bus";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ /* 15 reserved */
+
+ };
+
+ clk_sel_con2: sel-con@004c {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x004c 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ hclk_vio: hclk_vio_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 5>;
+ clocks = <&aclk_iep>;
+ clock-output-names = "hclk_vio";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ /* 7:5 reserved */
+
+ clk_nandc_div: clk_nandc_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 5>;
+ clocks = <&clk_nandc>;
+ clock-output-names = "clk_nandc";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* 13: reserved */
+
+ clk_nandc: clk_nandc_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <14 1>;
+ clocks = <&clk_cpll>, <&clk_gpll>;
+ clock-output-names = "clk_nandc";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ /* 15 reserved */
+
+ };
+
+ clk_sel_con3: sel-con@0050 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0050 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_i2s1_pll_div: clk_i2s1_pll_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 7>;
+ clocks = <&clk_i2s1_pll>;
+ clock-output-names = "clk_i2s1_pll";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
+ };
+
+ /* 7: reserved */
+
+ clk_i2s1: clk_i2s1_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <8 2>;
+ clocks = <&clk_i2s1_pll_div>, <&i2s1_frac>, <&i2s_clkin>, <&xin12m>;
+ clock-output-names = "clk_i2s1";
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_RK3288_I2S>;
+ rockchip,flags = <CLK_SET_RATE_PARENT>;
+ };
+
+ /* 11:10: reserved */
+
+ clk_i2s1_out: clk_i2s1_out_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <12 1>;
+ clocks = <&clk_i2s1>, <&xin12m>;
+ clock-output-names = "i2s_clkout";
+ #clock-cells = <0>;
+ };
+
+ /* 14:13: reserved */
+
+ clk_i2s1_pll: i2s1_pll_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <15 1>;
+ clocks = <&clk_cpll>,<&clk_gpll>;
+ clock-output-names = "clk_i2s1_pll";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ };
+
+ clk_sel_con4: sel-con@0054 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0054 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ testclk_div: testclk_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 5>;
+ clocks = <&testclk>;
+ clock-output-names = "testclk";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* 7:5 reserved */
+
+ clk_24m_div: clk_24m_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 5>;
+ clocks = <&xin24m>;
+ clock-output-names = "clk_24m";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* 15:13 reserved */
+
+ };
+
+ clk_sel_con5: sel-con@0058 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0058 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_mac_pll_div: clk_mac_pll_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 5>;
+ clocks = <&clk_mac_pll>;
+ clock-output-names = "clk_mac_pll";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ clk_mac: clk_mac_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <5 1>;
+ clocks = <&clk_mac_pll>, <&rmii_clkin>;
+ clock-output-names = "clk_mac";
+ #clock-cells = <0>;
+ rockchip,flags = <CLK_SET_RATE_PARENT>;
+ #clock-init-cells = <1>;
+ };
+
+ /* 6 reserved */
+
+ clk_mac_pll: clk_mac_pll_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <7 1>;
+ clocks = <&clk_cpll>, <&clk_gpll>;
+ clock-output-names = "clk_mac_pll";
+ #clock-cells = <0>;
+ };
+
+ clk_gmac_div: clk_gmac_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 5>;
+ clocks = <&clk_gmac>;
+ clock-output-names = "clk_gmac";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* 14:13 reserved */
+
+ clk_gmac: clk_gmac_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <15 1>;
+ clocks = <&clk_cpll>, <&clk_gpll>;
+ clock-output-names = "clk_gmac";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ };
+
+ clk_sel_con6: sel-con@005c {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x005c 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ spdif_div: spdif_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 7>;
+ clocks = <&clk_spdif_pll>;
+ clock-output-names = "clk_spdif_pll";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
+ };
+
+ /* 7 reserved */
+
+ clk_spdif: spdif_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <8 2>;
+ clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>;
+ clock-output-names = "clk_spdif";
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_RK3288_I2S>;
+ rockchip,flags = <CLK_SET_RATE_PARENT>;
+ };
+
+ /* 14:10 reserved */
+
+ clk_spdif_pll: spdif_pll_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <15 1>;
+ clocks = <&clk_cpll>,<&clk_gpll>;
+ clock-output-names = "clk_spdif_pll";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ };
+
+ clk_sel_con7: sel-con@0060 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0060 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ i2s1_frac: i2s1_frac {
+ compatible = "rockchip,rk3188-frac-con";
+ clocks = <&clk_i2s1_pll_div>;
+ clock-output-names = "i2s1_frac";
+ /* numerator denominator */
+ rockchip,bits = <0 32>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_FRAC>;
+ #clock-cells = <0>;
+ };
+
+ };
+
+ clk_sel_con8: sel-con@0064 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0064 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ i2s0_frac: i2s0_frac {
+ compatible = "rockchip,rk3188-frac-con";
+ clocks = <&clk_i2s0_pll_div>;
+ clock-output-names = "i2s0_frac";
+ /* numerator denominator */
+ rockchip,bits = <0 32>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_FRAC>;
+ #clock-cells = <0>;
+ };
+
+ };
+
+ clk_sel_con9: sel-con@0068 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0068 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_i2s0_pll_div: clk_i2s0_pll_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 7>;
+ clocks = <&clk_i2s0_pll>;
+ clock-output-names = "clk_i2s0_pll";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
+ };
+
+ /* 7: reserved */
+
+ clk_i2s0: clk_i2s0_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <8 2>;
+ clocks = <&clk_i2s0_pll_div>, <&i2s0_frac>, <&i2s_clkin>, <&xin12m>;
+ clock-output-names = "clk_i2s0";
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_RK3288_I2S>;
+ rockchip,flags = <CLK_SET_RATE_PARENT>;
+ };
+
+ /* 14:10: reserved */
+
+ clk_i2s0_pll: i2s0_pll_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <15 1>;
+ clocks = <&clk_cpll>,<&clk_gpll>;
+ clock-output-names = "clk_i2s0_pll";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ };
+
+ clk_sel_con10: sel-con@006c {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x006c 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aclk_peri_div: aclk_peri_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 5>;
+ clocks = <&aclk_peri>;
+ clock-output-names = "aclk_peri";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* 7:5: reserved */
+
+ hclk_peri: hclk_peri_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 2>;
+ clocks = <&aclk_peri>;
+ clock-output-names = "hclk_peri";
+ rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
+ rockchip,div-relations =
+ <0x0 1
+ 0x1 2
+ 0x2 4>;
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ aclk_peri: aclk_peri_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <10 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>;
+ clock-output-names = "aclk_peri";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ pclk_peri: pclk_peri_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <12 2>;
+ clocks = <&aclk_peri>;
+ clock-output-names = "pclk_peri";
+ rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
+ rockchip,div-relations =
+ <0x0 1
+ 0x1 2
+ 0x2 4
+ 0x3 8>;
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ /* 15: reserved */
+
+ };
+
+ clk_sel_con11: sel-con@0070 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0070 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_sdmmc0_div: clk_sdmmc0_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 8>;
+ clocks = <&clk_sdmmc0>;
+ clock-output-names = "clk_sdmmc0";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_EVENDIV>;
+ };
+
+ clk_sdmmc0: clk_sdmmc0_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <8 2>;
+ clocks = <&clk_cpll>,<&clk_gpll>,<&xin24m>,<&usb480m>;
+ clock-output-names = "clk_sdmmc0";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ clk_sdio: clk_sdio_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <10 2>;
+ clocks = <&clk_cpll>,<&clk_gpll>,<&xin24m>,<&usb480m>;
+ clock-output-names = "clk_sdio";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ clk_emmc: clk_emmc_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <12 2>;
+ clocks = <&clk_cpll>,<&clk_gpll>,<&xin24m>,<&usb480m>;
+ clock-output-names = "clk_emmc";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ /* 15:14 reserved */
+
+ };
+
+ clk_sel_con12: sel-con@0074 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0074 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_sdio_div: clk_sdio_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 8>;
+ clocks = <&clk_sdio>;
+ clock-output-names = "clk_sdio";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_EVENDIV>;
+ };
+
+ clk_emmc_div: clk_emmc_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 8>;
+ clocks = <&clk_emmc>;
+ clock-output-names = "clk_emmc";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_EVENDIV>;
+ };
+
+ };
+
+ clk_sel_con13: sel-con@0078 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0078 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_uart0_pll_div: clk_uart0_pll_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 7>;
+ clocks = <&clk_uart0_pll>;
+ clock-output-names = "clk_uart0_pll";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ };
+
+ /* 7 reserved */
+
+ clk_uart0: clk_uart0_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <8 2>;
+ clocks = <&clk_uart0_pll_div>, <&uart0_frac>, <&xin24m>;
+ clock-output-names = "clk_uart0";
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_RK3288_I2S>;
+ rockchip,flags = <CLK_SET_RATE_PARENT>;
+ };
+
+ /* 11:10 reserved */
+
+ clk_uart0_pll: clk_uart0_pll_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <12 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&usb480m>;
+ clock-output-names = "clk_uart0_pll";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ /* 15:14 reserved */
+
+ };
+
+ clk_sel_con14: sel-con@007c {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x007c 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_uart1_pll_div: clk_uart1_pll_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 7>;
+ clocks = <&clk_uart1_pll>;
+ clock-output-names = "clk_uart1_pll";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ };
+
+ /* 7 reserved */
+
+ clk_uart1: clk_uart1_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <8 2>;
+ clocks = <&clk_uart1_pll_div>, <&uart1_frac>, <&xin24m>;
+ clock-output-names = "clk_uart1";
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_RK3288_I2S>;
+ rockchip,flags = <CLK_SET_RATE_PARENT>;
+ };
+
+ /* 11:10 reserved */
+
+ clk_uart1_pll: clk_uart1_pll_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <12 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&usb480m>;
+ clock-output-names = "clk_uart1_pll";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ /* 15:14 reserved */
+ };
+
+ clk_sel_con15: sel-con@0080 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0080 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_uart2_pll_div: clk_uart2_pll_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 7>;
+ clocks = <&clk_uart2_pll>;
+ clock-output-names = "clk_uart2_pll";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ };
+
+ /* 7 reserved */
+
+ clk_uart2: clk_uart2_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <8 2>;
+ clocks = <&clk_uart2_pll>, <&uart2_frac>, <&xin24m>;
+ clock-output-names = "clk_uart2";
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_RK3288_I2S>;
+ rockchip,flags = <CLK_SET_RATE_PARENT>;
+ };
+
+ /* 11:10 reserved */
+
+ clk_uart2_pll: clk_uart2_pll_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <12 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&usb480m>;
+ clock-output-names = "clk_uart2_pll";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ /* 15:14 reserved */
+
+ };
+
+ clk_sel_con16: sel-con@0084 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0084 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ i2s2_pll_div: i2s2_pll_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 7>;
+ clocks = <&clk_i2s2_pll>;
+ clock-output-names = "clk_i2s2_pll";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_MUX_DIV>;
+ rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
+ };
+
+ /* 7: reserved */
+
+ clk_i2s2: clk_i2s2_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <8 2>;
+ clocks = <&i2s2_pll_div>, <&i2s2_frac>, <&i2s_clkin>, <&xin12m>;
+ clock-output-names = "clk_i2s2";
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_RK3288_I2S>;
+ rockchip,flags = <CLK_SET_RATE_PARENT>;
+ };
+
+ /* 14:10: reserved */
+
+ clk_i2s2_pll: i2s2_pll_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <15 1>;
+ clocks = <&clk_cpll>,<&clk_gpll>;
+ clock-output-names = "clk_i2s2_pll";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ };
+
+ clk_sel_con17: sel-con@0088 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0088 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0_frac: uart0_frac {
+ compatible = "rockchip,rk3188-frac-con";
+ clocks = <&clk_uart0_pll_div>;
+ clock-output-names = "uart0_frac";
+ /* numerator denominator */
+ rockchip,bits = <0 32>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_FRAC>;
+ #clock-cells = <0>;
+ };
+
+ };
+
+ clk_sel_con18: sel-con@008c {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x008c 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart1_frac: uart1_frac {
+ compatible = "rockchip,rk3188-frac-con";
+ clocks = <&clk_uart1_pll_div>;
+ clock-output-names = "uart1_frac";
+ /* numerator denominator */
+ rockchip,bits = <0 32>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_FRAC>;
+ #clock-cells = <0>;
+ };
+
+ };
+
+ clk_sel_con19: sel-con@0090 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0090 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart2_frac: uart2_frac {
+ compatible = "rockchip,rk3188-frac-con";
+ clocks = <&clk_uart2_pll_div>;
+ clock-output-names = "uart2_frac";
+ /* numerator denominator */
+ rockchip,bits = <0 32>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_FRAC>;
+ #clock-cells = <0>;
+ };
+
+ };
+
+ clk_sel_con20: sel-con@0094 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0094 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ spdif_frac: spdif_frac {
+ compatible = "rockchip,rk3188-frac-con";
+ clocks = <&spdif_div>;
+ clock-output-names = "spdif_frac";
+ /* numerator denominator */
+ rockchip,bits = <0 32>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_FRAC>;
+ #clock-cells = <0>;
+ };
+
+ };
+
+ clk_sel_con21: sel-con@0098 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0098 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_hdmi_cec: clk_hdmi_cec_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 14>;
+ clocks = <&xin24m>;
+ clock-output-names = "clk_hdmi_cec";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
+ };
+ /*
+ clk_hdmi_cec_div: clk_hdmi_cec_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 14>;
+ clocks = <&clk_hdmi_cec>;
+ clock-output-names = "clk_hdmi_cec";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ clk_hdmi_cec: clk_hdmi_cec_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <14 2>;
+ clocks = <&dummy>, <&dummy>, <&xin24m>;
+ clock-output-names = "clk_hdmi_cec";
+ #clock-cells = <0>;
+ };
+ */
+ };
+
+ clk_sel_con22: sel-con@009c {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x009c 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_rga: clk_rga_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 5>;
+ clocks = <&aclk_rga>;
+ clock-output-names = "clk_rga";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* 7:0 reserved */
+
+ clk_tsp_div: clk_tsp_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 5>;
+ clocks = <&clk_tsp>;
+ clock-output-names = "clk_tsp";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* 14:13 reserved */
+
+ clk_tsp: clk_tsp_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <15 1>;
+ clocks = <&clk_cpll>, <&clk_gpll>;
+ clock-output-names = "clk_tsp";
+ #clock-cells = <0>;
+ };
+
+ };
+
+ clk_sel_con23: sel-con@00a0 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00a0 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_wifi_div: clk_wifi_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 5>;
+ clocks = <&clk_wifi>;
+ clock-output-names = "clk_wifi";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ clk_wifi: clk_wifi_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <5 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&usb480m>;
+ clock-output-names = "clk_wifi";
+ #clock-cells = <0>;
+ };
+
+ /* 7 reserved */
+
+ clk_hdcp_div: clk_hdcp_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 6>;
+ clocks = <&clk_hdcp>;
+ clock-output-names = "clk_hdcp";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ clk_hdcp: clk_hdcp_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <14 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>;
+ clock-output-names = "clk_hdcp";
+ #clock-cells = <0>;
+ };
+
+ };
+
+ clk_sel_con24: sel-con@00a4 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00a4 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_crypto_div: clk_crypto_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 5>;
+ clocks = <&clk_crypto>;
+ clock-output-names = "clk_crypto";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ clk_crypto: clk_crypto_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <5 1>;
+ clocks = <&clk_cpll>, <&clk_gpll>;
+ clock-output-names = "clk_crypto";
+ #clock-cells = <0>;
+ };
+
+ clk_tsadc: clk_tsadc_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <6 10>;
+ clocks = <&xin24m>;
+ clock-output-names = "clk_tsadc";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ };
+
+ clk_sel_con25: sel-con@00a8 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00a8 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_spi0_div: clk_spi0_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 7>;
+ clocks = <&clk_spi0>;
+ clock-output-names = "clk_spi0";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* 7 reserved */
+
+ clk_spi0: clk_spi0_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <8 1>;
+ clocks = <&clk_cpll>, <&clk_gpll>;
+ clock-output-names = "clk_spi0";
+ #clock-cells = <0>;
+ };
+
+ /* 15:9 reserved */
+
+ };
+
+ clk_sel_con26: sel-con@00ac {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00ac 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk_ddr_div: clk_ddr_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 2>;
+ clocks = <&clk_ddr>;
+ clock-output-names = "clk_ddr";
+ rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
+ rockchip,div-relations =
+ <0x0 1
+ 0x1 2
+ 0x3 4>;
+ #clock-cells = <0>;
+ rockchip,flags = <(CLK_GET_RATE_NOCACHE |
+ CLK_SET_RATE_NO_REPARENT)>;
+ rockchip,clkops-idx = <CLKOPS_RATE_DDR_DIV2>;
+ };
+
+ /* 7:2 reserved */
+
+ clk_ddr: clk_ddr_pll_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <8 2>;
+ clocks = <&clk_dpll>, <&clk_gpll>, <&clk_apll>;
+ clock-output-names = "clk_ddr";
+ #clock-cells = <0>;
+ };
+
+ /* 15:10 reserved */
+
+ };
+
+ clk_sel_con27: sel-con@00b0 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00b0 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ dclk_vop0_pll: dclk_vop0_pll_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <0 1>;
+ clocks = <&clk_gpll>, <&clk_cpll>;
+ clock-output-names = "dclk_vop0_pll";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ dclk_vop0: dclk_vop0_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <1 1>;
+ clocks = <&hdmi_phy_clk>, <&dummy>;/*dclk_vop0_div*/
+ clock-output-names = "dclk_vop0";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ /* 7:2 reserved */
+
+ dclk_vop0_div: dclk_vop0_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 8>;
+ clocks = <&dclk_vop0_pll>;
+ clock-output-names = "dclk_vop0";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ };
+
+ clk_sel_con28: sel-con@00b4 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00b4 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aclk_rkvdec_div: aclk_rkvdec_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 5>;
+ clocks = <&aclk_rkvdec>;
+ clock-output-names = "aclk_rkvdec";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* 5 reserved */
+
+ aclk_rkvdec: aclk_rkvdec_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <6 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
+ clock-output-names = "aclk_rkvdec";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ clk_vdec_cabac_div: clk_vdec_cabac_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 5>;
+ clocks = <&clk_vdec_cabac>;
+ clock-output-names = "clk_vdec_cabac";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* 13 reserved */
+
+ clk_vdec_cabac: clk_vdec_cabac_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <14 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
+ clock-output-names = "clk_vdec_cabac";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+ };
+
+ clk_sel_con29: sel-con@00b8 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00b8 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ dclk_hdmiphy_div: dclk_hdmiphy_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 3>;
+ clocks = <&dclk_vop0_pll>;
+ clock-output-names = "dclk_hdmiphy";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ /* 7:3 reserved */
+
+ clk_macphy_div: clk_macphy_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 3>;
+ clocks = <&clk_macphy>;
+ clock-output-names = "clk_macphy";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ rmii_clkin: rmii_clkin {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <10 1>;
+ clocks = <&gmac_clkin>, <&phy_50m_out>;
+ clock-output-names = "rmii_clkin";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+ /*
+ clk_mac_tx: clk_mac_tx {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <11 1>;
+ clocks = <&clk_gates5 6>, <&phy_tx_out>;
+ clock-output-names = "clk_mac_tx";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+ */
+ clk_macphy: clk_macphy_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <12 1>;
+ clocks = <&clk_mac_pll_div>, <&gmac_clkin>;
+ clock-output-names = "clk_macphy";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ /* 15:13 reserved */
+
+ };
+
+ clk_sel_con30: sel-con@00bc {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00bc 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ i2s2_frac: i2s2_frac {
+ compatible = "rockchip,rk3188-frac-con";
+ clocks = <&i2s2_pll_div>;
+ clock-output-names = "i2s2_frac";
+ /* numerator denominator */
+ rockchip,bits = <0 32>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_FRAC>;
+ #clock-cells = <0>;
+ };
+ };
+
+ clk_sel_con31: sel-con@00c0 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00c0 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aclk_iep_div: aclk_iep_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 5>;
+ clocks = <&aclk_iep>;
+ clock-output-names = "aclk_iep";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ aclk_iep: aclk_iep_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <5 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
+ clock-output-names = "aclk_iep";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ /* 7: reserved */
+
+ aclk_hdcp_div: aclk_hdcp_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 5>;
+ clocks = <&aclk_hdcp>;
+ clock-output-names = "aclk_hdcp";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ aclk_hdcp: aclk_hdcp_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <13 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
+ clock-output-names = "aclk_hdcp";
+ #clock-cells = <0>;
+ };
+
+ /* 15: reserved */
+ };
+
+ clk_sel_con32: sel-con@00c4 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00c4 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aclk_vpu_div: aclk_vpu_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 5>;
+ clocks = <&aclk_vpu>;
+ clock-output-names = "aclk_vpu";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ aclk_vpu: aclk_vpu_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <5 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
+ clock-output-names = "aclk_vpu";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ /* 15:7 reserved */
+
+ };
+
+ clk_sel_con33: sel-con@00c8 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00c8 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aclk_vop_div: aclk_vop_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 5>;
+ clocks = <&aclk_vop>;
+ clock-output-names = "aclk_vop";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ aclk_vop: aclk_vop_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <5 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
+ clock-output-names = "aclk_vop";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ /* 7 reserved */
+
+ aclk_rga_div: aclk_rga_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 5>;
+ clocks = <&aclk_rga>;
+ clock-output-names = "aclk_rga";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ aclk_rga: aclk_rga_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <13 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
+ clock-output-names = "aclk_rga";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ /* 15 reserved */
+
+ };
+
+ clk_sel_con34: sel-con@00cc {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x00cc 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aclk_gpu_div: aclk_gpu_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <0 5>;
+ clocks = <&aclk_gpu>;
+ clock-output-names = "aclk_gpu";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ aclk_gpu: aclk_gpu_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <5 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
+ clock-output-names = "aclk_gpu";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ /* 7 reserved */
+
+ clk_vdec_core_div: clk_vdec_core_div {
+ compatible = "rockchip,rk3188-div-con";
+ rockchip,bits = <8 5>;
+ clocks = <&clk_vdec_core>;
+ clock-output-names = "clk_vdec_core";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
+ #clock-cells = <0>;
+ rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
+ };
+
+ clk_vdec_core: clk_vdec_core_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <13 2>;
+ clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
+ clock-output-names = "clk_vdec_core";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+
+ };
+
+ /* 15 reserved */
+ };
+
+ clk_sel_con35: sel-con@0134 {
+ compatible = "rockchip,rk3188-selcon";
+ reg = <0x0134 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* 7:0 reserved */
+
+ testclk: testclk_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <8 4>;
+ clocks = <&clk_wifi>, <&dummy>, <&clk_core>, <&clk_gates7 0>, <&aclk_iep>, <&aclk_gpu>, <&aclk_peri>, <&aclk_core>;
+ clock-output-names = "testclk";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ /* 12 reserved */
+
+ hdmi_phy_clk: hdmi_phy_clk_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <13 1>;
+ clocks = <&hdmiphy_out>, <&xin24m>;
+ clock-output-names = "hdmi_phy_clk";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ usb480m_phy: usb480m_phy_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <14 1>;
+ clocks = <&usbphy0_480m>, <&usbphy1_480m>;
+ clock-output-names = "usb480m_phy";
+ #clock-cells = <0>;
+ #clock-init-cells = <1>;
+ };
+
+ usb480m: usb480m_mux {
+ compatible = "rockchip,rk3188-mux-con";
+ rockchip,bits = <15 1>;
+ clocks = <&usb480m_phy>, <&xin24m>;
+ clock-output-names = "usb480m";
+ #clock-cells = <0>;
+ rockchip,clkops-idx =
+ <CLKOPS_RATE_RK3288_USB480M>;
+ #clock-init-cells = <1>;
+ };
+ };
+ };
+ /* Gate control regs */
+ clk_gate_cons {
+ compatible = "rockchip,rk-gate-cons";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clk_gates0: gate-clk@00d0 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x00d0 0x4>;
+ clocks =
+ <&dummy>, <&dummy>,
+ <&dummy>, <&clk_i2s0_pll>,
+
+ <&i2s0_frac>, <&clk_i2s0>,
+ <&dummy>, <&clk_i2s2_pll>,
+
+ <&i2s2_frac>, <&clk_i2s2>,
+ <&clk_i2s1_pll>, <&i2s1_frac>,
+
+ <&dummy>, <&clk_i2s1_out>,
+ <&clk_i2s1>, <&testclk>;
+
+ clock-output-names =
+ "reserved", "reserved",
+ "reserved", "clk_i2s0_pll",
+
+ "i2s0_frac", "i2s0_8ch",
+ "reserved", "clk_i2s2_pll",
+
+ "i2s2_frac", "i2s2_2ch",
+ "clk_i2s1_pll", "i2s1_frac",
+
+ "reserved", "i2s_clkout",
+ "i2s1_8ch", "testclk";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates1: gate-clk@00d4 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x00d4 0x4>;
+ clocks =
+ <&clk_nandc>, <&aclk_vop>,
+ <&aclk_rga>, <&jtag_clkin>,
+
+ <&aclk_hdcp>, <&xin24m>,
+ <&xin24m>, <&clk_mac_pll>,
+
+ <&clk_uart0_pll>, <&uart0_frac>,
+ <&clk_uart1_pll>, <&uart1_frac>,
+
+ <&clk_uart2_pll>, <&uart2_frac>,
+ <&dummy>, <&dummy>;
+
+ clock-output-names =
+ "clk_nandc", "aclk_vop",
+ "aclk_rga", "clk_jtag",
+
+ "aclk_hdcp", "clk_otgphy0",
+ "clk_otgphy1", "clk_mac_pll",
+
+ "clk_uart0_pll", "uart0_frac",
+ "clk_uart1_pll", "uart1_frac",
+
+ "clk_uart2_pll", "uart2_frac",
+ "reserved", "reserved";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates2: gate-clk@00d8 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x00d8 0x4>;
+ clocks =
+ <&dummy>, <&dummy>,
+ <&clk_gmac>, <&dummy>,
+
+ <&dummy>, <&dummy>,
+ <&clk_tsp>, <&clk_crypto>,
+
+ <&clk_tsadc>, <&clk_spi0>,
+ <&clk_spdif_pll>, <&clk_sdmmc0>,
+
+ <&spdif_frac>, <&clk_sdio>,
+ <&clk_emmc>, <&clk_wifi>;
+
+ clock-output-names =
+ "reserved", "clk_ddrmon",
+ "clk_gmac", "reserved",
+
+ "reserved", "reserved",
+ "clk_tsp", "clk_crypto",
+
+ "clk_tsadc", "clk_spi0",
+ "clk_spdif_pll", "clk_sdmmc0",
+
+ "spdif_frac", "clk_sdio",
+ "clk_emmc", "clk_wifi";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates3: gate-clk@00dc {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x00dc 0x4>;
+ clocks =
+ <&aclk_iep>, <&dummy>,
+ <&aclk_rkvdec>, <&clk_vdec_cabac>,
+
+ <&clk_vdec_core>, <&clk_hdcp>,
+ <&aclk_rga>, <&xin24m>,
+
+ <&clk_hdmi_cec>, <&dummy>,
+ <&dummy>, <&aclk_vpu>,
+
+ <&dummy>, <&dummy>,
+ <&dummy>, <&dummy>;
+
+ clock-output-names =
+ "aclk_iep", "dclk_vop0",
+ "aclk_rkvdec", "clk_vdec_cabac",
+
+ "clk_vdec_core", "clk_hdcp",
+ "clk_rga", "clk_hdmi_hdcp",
+
+ "clk_hdmi_cec", "reserved",
+ "reserved", "aclk_vpu",
+
+ "reserved", "reserved",
+ "reserved", "reserved";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates4: gate-clk@00e0 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x00e0 0x4>;
+ clocks =
+ <&clk_core>, <&clk_core>,
+ <&aclk_core>, <&dummy>,
+
+ <&aclk_vpu>, <&aclk_rkvdec>,
+ <&dummy>, <&dummy>,
+
+ <&dummy>, <&dummy>,
+ <&dummy>, <&dummy>,
+
+ <&dummy>, <&dummy>,
+ <&dummy>, <&dummy>;
+
+ clock-output-names =
+ "aclk_core", "pclk_dbg",
+ "aclk_gic400", "reserved",
+
+ "hclk_vpu", "hclk_rkvdec",
+ "reserved", "reserved",
+
+ "reserved", "reserved",
+ "reserved", "reserved",
+
+ "reserved", "reserved",
+ "reserved", "reserved";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates5: gate-clk@00e4 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x00e4 0x4>;
+ clocks =
+ <&aclk_peri>, <&aclk_peri>,
+ <&aclk_peri>, <&clk_mac>,
+
+ <&clk_mac>, <&clk_mac>,
+ <&clk_mac>, <&clk_macphy>,
+
+ <&dummy>, <&dummy>,
+ <&dummy>, <&dummy>,
+
+ <&dummy>, <&dummy>,
+ <&dummy>, <&dummy>;
+
+ clock-output-names =
+ "aclk_peri", "hclk_peri",
+ "pclk_peri", "clk_mac_ref",
+
+ "clk_mac_refout", "clk_mac_rx",
+ "clk_mac_tx", "clk_macphy",
+
+ "reserved", "reserved",
+ "reserved", "reserved",
+
+ "reserved", "reserved",
+ "reserved", "reserved";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates6: gate-clk@00e8 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x00e8 0x4>;
+ clocks =
+ <&aclk_bus>, <&aclk_bus>,
+ <&aclk_bus>, <&pclk_bus>,
+
+ <&pclk_bus>, <&xin24m>,
+ <&xin24m>, <&xin24m>,
+
+ <&xin24m>, <&xin24m>,
+ <&xin24m>, <&dummy>,
+
+ <&dummy>, <&pclk_bus>,
+ <&dummy>, <&dummy>;
+
+ clock-output-names =
+ "aclk_bus", "hclk_bus",
+ "pclk_bus", "pclk_bus_pre",
+
+ "pclk_phy", "clk_timer0",
+ "clk_timer1", "clk_timer2",
+
+ "clk_timer3", "clk_timer4",
+ "clk_timer5", "reserved",
+
+ "reserved", "pclk_ddr",
+ "reserved", "reserved";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates7: gate-clk@00ec {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x00ec 0x4>;
+ clocks =
+ <&clk_ddr_div>, <&clk_ddr_div>,
+ <&dummy>, <&dummy>,
+
+ <&dummy>, <&dummy>,
+ <&dummy>, <&dummy>,
+
+ <&dummy>, <&dummy>,
+ <&dummy>, <&dummy>,
+
+ <&dummy>, <&dummy>,
+ <&aclk_gpu>, <&aclk_gpu>;
+
+ clock-output-names =
+ "clk_ddrphy", "clk4x_ddrphy",
+ "reserved", "reserved",
+
+ "reserved", "reserved",
+ "reserved", "reserved",
+
+ "reserved", "reserved",
+ "reserved", "reserved",
+
+ "reserved", "reserved",
+ "g_aclk_gpu", "g_aclk_gpu_noc";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates8: gate-clk@00f0 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x00f0 0x4>;
+ clocks =
+ <&aclk_bus>, <&aclk_bus>,
+ <&aclk_bus>, <&hclk_bus>,
+
+ <&clk_gates6 13>, <&clk_gates7 0>,
+ <&clk_gates6 13>, <&hclk_bus>,
+
+ <&hclk_bus>, <&hclk_bus>,
+ <&hclk_bus>, <&hclk_bus>,
+
+ <&hclk_bus>, <&pclk_bus>,
+ <&pclk_bus>, <&pclk_bus>;
+
+ clock-output-names =
+ "g_aclk_intmem", "g_intmem_mbist",
+ "g_aclk_dmac_bus", "g_hclk_rom",
+
+ "g_p_ddrupctl", "g_clk_ddrupctl",
+ "g_p_ddrmon", "g_h_i2s0_8ch",
+
+ "g_h_i2s1_8ch", "g_h_i2s2_2ch",
+ "g_h_spdif_8ch", "g_h_crypto_mst",
+
+ "g_h_crypto_slv", "g_p_efuse_1024",
+ "g_p_efuse_256", "g_pclk_i2c0";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates9: gate-clk@00f4 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x00f4 0x4>;
+ clocks =
+ <&pclk_bus>, <&pclk_bus>,
+ <&pclk_bus>, <&dummy>,
+
+ <&pclk_bus>, <&pclk_bus>,
+ <&pclk_bus>, <&pclk_bus>,
+
+ <&pclk_bus>, <&pclk_bus>,
+ <&pclk_bus>, <&pclk_bus>,
+
+ <&pclk_bus>, <&pclk_bus>,
+ <&pclk_bus>, <&pclk_bus>;
+
+ clock-output-names =
+ "g_pclk_i2c1", "g_pclk_i2c2",
+ "g_pclk_i2c3", "reserved",
+
+ "g_pclk_timer0", "g_pclk_stimer",
+ "g_pclk_spi0", "g_pclk_rk_pwm",
+
+ "g_pclk_gpio0", "g_pclk_gpio1",
+ "g_pclk_gpio2", "g_pclk_gpio3",
+
+ "g_pclk_uart0", "g_pclk_uart1",
+ "g_pclk_uart2", "g_pclk_tsadc";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates10: gate-clk@00f8 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x00f8 0x4>;
+ clocks =
+ <&pclk_bus>, <&aclk_bus>,
+ <&clk_gates6 13>, <&clk_gates6 4>,
+
+ <&pclk_bus>, <&clk_gates6 4>,
+ <&pclk_bus>, <&clk_gates6 4>,
+
+ <&clk_gates6 4>, <&clk_gates6 4>,
+ <&pclk_bus>, <&hclk_bus>,
+
+ <&clkin_hsadc_tsp>, <&dummy>,
+ <&dummy>, <&dummy>;
+
+ clock-output-names =
+ "g_pclk_grf", "g_aclk_bus",
+ "g_p_mschniu", "g_p_ddrphy",
+
+ "g_pclk_cru", "g_p_acodecphy",
+ "g_pclk_sgrf", "g_p_hdmiphy",
+
+ "g_p_vdacphy", "g_p_phy_noc",
+ "g_pclk_sim", "g_hclk_tsp",
+
+ "clk_hsadc_tsp", "reserved",
+ "reserved", "reserved";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates11: gate-clk@00fc {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x00fc 0x4>;
+ clocks =
+ <&hclk_peri>, <&hclk_peri>,
+ <&hclk_peri>, <&hclk_peri>,
+
+ <&aclk_peri>, <&pclk_peri>,
+ <&hclk_peri>, <&hclk_peri>,
+
+ <&hclk_peri>, <&hclk_peri>,
+ <&hclk_peri>, <&dummy>,
+
+ <&hclk_peri>, <&hclk_peri>,
+ <&hclk_peri>, <&dummy>;
+
+ clock-output-names =
+ "g_hclk_sdmmc", "g_hclk_sdio",
+ "g_clk_emmc", "g_clk_nandc",
+
+ "g_aclk_gmac", "g_pclk_gmac",
+ "g_hclk_host0", "g_h_host0_arb",
+
+ "g_hclk_host1", "g_h_host1_arb",
+ "g_hclk_host2", "reserved",
+
+ "g_hclk_otg", "g_hclk_otg_pmu",
+ "g_h_host2_arb", "reserved";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates12: gate-clk@0100 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x0100 0x4>;
+ clocks =
+ <&aclk_peri>, <&hclk_peri>,
+ <&pclk_peri>, <&dummy>,
+
+ <&dummy>, <&dummy>,
+ <&dummy>, <&dummy>,
+
+ <&dummy>, <&dummy>,
+ <&dummy>, <&dummy>,
+
+ <&dummy>, <&dummy>,
+ <&dummy>, <&dummy>;
+
+ clock-output-names =
+ "g_a_peri_noc", "g_h_peri_noc",
+ "g_p_peri_noc", "reserved",
+
+ "reserved", "reserved",
+ "reserved", "reserved",
+
+ "reserved", "reserved",
+ "reserved", "reserved",
+
+ "reserved", "reserved",
+ "reserved", "reserved";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates13: gate-clk@0104 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x0104 0x4>;
+ clocks =
+ <&aclk_rga>, <&hclk_vio>,
+ <&aclk_iep>, <&hclk_vio>,
+
+ <&dummy>, <&aclk_vop>,
+ <&hclk_vio>, <&hclk_vio>,
+
+ <&hclk_vio>, <&aclk_iep>,
+ <&aclk_hdcp>, <&aclk_rga>,
+
+ <&aclk_vop>, <&hclk_vio>,
+ <&dummy>, <&dummy>;
+
+ clock-output-names =
+ "g_aclk_rga", "g_hclk_rga",
+ "g_aclk_iep", "g_hclk_iep",
+
+ "reserved", "g_aclk_vop",
+ "g_hclk_vop", "g_h_vio_ahbarbi",
+
+ "g_h_vio_noc", "g_a_iep_noc",
+ "g_a_hdcp_noc", "g_a_rga_noc",
+
+ "g_a_vop_noc", "g_h_vop_noc",
+ "reserved", "reserved";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates14: gate-clk@0108 {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x0108 0x4>;
+ clocks =
+ <&dummy>, <&dummy>,
+ <&dummy>, <&dummy>,
+
+ <&dummy>, <&dummy>,
+ <&hclk_vio>, <&hclk_vio>,
+
+ <&dummy>, <&dummy>,
+ <&aclk_hdcp>, <&hclk_vio>,
+
+ <&hclk_vio>, <&dummy>,
+ <&dummy>, <&dummy>;
+
+ clock-output-names =
+ "reserved", "reserved",
+ "reserved", "reserved",
+
+ "reserved", "reserved",
+ "g_p_hdmi_ctrl", "g_h_vio_h2p",
+
+ "reserved", "reserved",
+ "g_aclk_hdcp", "g_pclk_hdcp",
+
+ "g_h_hdcp_mmu", "reserved",
+ "reserved", "reserved";
+
+ #clock-cells = <1>;
+ };
+
+ clk_gates15: gate-clk@010c {
+ compatible = "rockchip,rk3188-gate-clk";
+ reg = <0x010c 0x4>;
+ clocks =
+ <&aclk_vpu>, <&hclk_vpu>,
+ <&aclk_rkvdec>, <&hclk_rkvdec>,
+
+ <&aclk_vpu>, <&hclk_vpu>,
+ <&aclk_rkvdec>, <&hclk_rkvdec>,
+
+ <&dummy>, <&dummy>,
+ <&dummy>, <&dummy>,
+
+ <&dummy>, <&dummy>,
+ <&dummy>, <&dummy>;
+
+ clock-output-names =
+ "g_aclk_vpu", "g_hclk_vpu",
+ "g_a_rkvdec", "g_h_rkvdec",
+
+ "g_a_vpu_noc", "g_h_vpu_noc",
+ "g_a_rkvdec_noc", "g_h_rkvdec_noc",
+
+ "reserved", "reserved",
+ "reserved", "reserved",
+
+ "reserved", "reserved",
+ "reserved", "reserved";
+
+ #clock-cells = <1>;
+ };
+ };
+ };
+};
+};
projects / firefly-linux-kernel-4.4.55.git / commitdiff