@echo ' Image: kernel.img (with $*.dtb) is ready'
LOGO := $(notdir $(wildcard $(srctree)/logo.bmp))
+LOGO_KERNEL := $(notdir $(wildcard $(srctree)/logo_kernel.bmp))
%.img: %.dtb kernel.img $(LOGO)
- $(Q)$(srctree)/resource_tool $(objtree)/arch/arm/boot/dts/$*.dtb $(LOGO)
- @echo ' Image: resource.img (with $*.dtb $(LOGO)) is ready'
+ $(Q)$(srctree)/resource_tool $(objtree)/arch/arm/boot/dts/$*.dtb $(LOGO) $(LOGO_KERNEL)
+ @echo ' Image: resource.img (with $*.dtb $(LOGO) $(LOGO_KERNEL)) is ready'
rockchip,usb-mode = <0>;
};
- usb1: usb@101c0000 {
- compatible = "rockchip,rk3126_usb20_host";
- reg = <0x101c0000 0x40000>;
+ ehci: usb@101c0000 {
+ compatible = "rockchip,rk3126_ehci";
+ reg = <0x101c0000 0x20000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_gates1 6>, <&clk_gates10 14>;
- clock-names = "clk_usbphy1", "hclk_usb1";
+ clocks = <&clk_gates1 6>, <&clk_gates7 3>, <&clk_gates10 14>;
+ clock-names = "clk_usbphy1", "hclk_hoct0_3126","hclk_host0_3126b";
resets = <&reset RK3128_RST_USBOTG1>, <&reset RK3128_RST_UTMI1>,
<&reset RK3128_RST_OTGC1>;
reset-names = "host_ahb", "host_phy", "host_controller";
};
+ ohci: usb@101e0000 {
+ compatible = "rockchip,rk3126_ohci";
+ reg = <0x101e0000 0x20000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
fb: fb{
compatible = "rockchip,rk-fb";
rockchip,disp-mode = <ONE_DUAL>;
&sdmmc0_vdd_domain{
regulator-name = "vcc_sd";
};
-&ion_cma {
- reg = <0x40000000 0x20000000>; /* 512MB */
-};
&sdmmc0_vdd_domain{
regulator-name = "vcc_sd";
};
-&ion_cma {
- reg = <0x40000000 0x20000000>; /* 512MB */
-};
regulator-name = "vcc_sd";
};
-&ion_cma {
- reg = <0x40000000 0x28000000>; /* 640MB */
-};
-
&dwc_control_usb {
usb_uart {
status = "disabled";
regulator-name = "vcc_sd";
};
-&ion_cma {
- reg = <0x40000000 0x28000000>; /* 640MB */
-};
-
&dwc_control_usb {
usb_uart {
status = "disabled";
ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
compatible = "rockchip,ion-heap";
rockchip,ion_heap = <1>;
- reg = <0x00000000 0x20000000>; /* 512MB */
+ reg = <0x00000000 0x28000000>; /* 640MB */
};
rockchip,ion-heap@3 { /* VMALLOC HEAP */
compatible = "rockchip,ion-heap";
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates13 5>, <&clk_gates7 6>;
clock-names = "clk_usbphy3", "hclk_usb3";
+ status = "disabled";
};
hsic: hsic@ff5c0000 {
CONFIG_CAMSYS_DRV=y
CONFIG_FLASHLIGHT=y
CONFIG_LEDS_RT8547=y
-# CONFIG_RK30_CAMERA_ONEFRAME is not set
+CONFIG_RK30_CAMERA_ONEFRAME=y
CONFIG_MALI_MIDGARD=m
CONFIG_MALI_MIDGARD_DVFS=y
CONFIG_MALI_MIDGARD_RT_PM=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_RK=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_RK=y
CONFIG_USB_ACM=y
CONFIG_USB_PRINTER=y
CONFIG_USB_STORAGE=y
#endif
#include <linux/rockchip/common.h>
#include <linux/rockchip/pmu.h>
+#include <linux/memblock.h>
#include "cpu_axi.h"
#include "loader.h"
#include "sram.h"
return 1;
}
__setup("rockchip_jtag", rockchip_jtag_enable);
+
+phys_addr_t uboot_logo_base=0;
+phys_addr_t uboot_logo_size=0;
+phys_addr_t uboot_logo_offset=0;
+
+void __init rockchip_uboot_mem_reserve(void)
+{
+ if (uboot_logo_size) {
+ if (!memblock_is_region_reserved(uboot_logo_base, uboot_logo_size)
+ && !memblock_reserve(uboot_logo_base, uboot_logo_size)){
+ pr_info("%s: reserve %zx@%zx for uboot logo\n", __func__,
+ uboot_logo_size, uboot_logo_base);
+ } else {
+ pr_err("%s: reserve of %zx@%zx failed\n", __func__,
+ uboot_logo_size, uboot_logo_base);
+ }
+ }
+}
+
+static int __init rockchip_uboot_logo_setup(char *p)
+{
+ char *endp;
+
+ uboot_logo_size = memparse(p, &endp);
+ if (*endp == '@') {
+ uboot_logo_base = memparse(endp + 1, &endp);
+ if (*endp == ':') {
+ uboot_logo_offset = memparse(endp + 1, NULL);
+ }
+ }
+
+ pr_info("%s: mem: %zx@%zx, offset:%zx\n", __func__,
+ uboot_logo_size, uboot_logo_base, uboot_logo_offset);
+
+ return 0;
+}
+early_param("uboot_logo", rockchip_uboot_logo_setup);
+
+static int __init rockchip_uboot_mem_late_init(void)
+{
+ phys_addr_t addr = 0;
+ phys_addr_t end = 0;
+
+ if (uboot_logo_size) {
+ addr = PAGE_ALIGN(uboot_logo_base);
+ end = (uboot_logo_base+uboot_logo_size)&PAGE_MASK;
+
+ pr_info("%s: Freeing uboot logo memory: %zx@%zx\n", __func__,
+ uboot_logo_size, uboot_logo_base);
+
+ memblock_free(uboot_logo_base, uboot_logo_size);
+
+ for (; addr < end; addr += PAGE_SIZE)
+ free_reserved_page(pfn_to_page(addr >> PAGE_SHIFT));
+ }
+
+ return 0;
+}
+late_initcall(rockchip_uboot_mem_late_init);
static void __init rk312x_reserve(void)
{
+ /* reserve memory for uboot */
+ rockchip_uboot_mem_reserve();
+
/* reserve memory for ION */
rockchip_ion_reserve();
}
static void __init rk3288_reserve(void)
{
+ /* reserve memory for uboot */
+ rockchip_uboot_mem_reserve();
+
/* reserve memory for ION */
rockchip_ion_reserve();
}
static u32 clk_gcd(u32 numerator, u32 denominator)
{
- u32 a, b;
-
- if (!numerator || !denominator)
- return 0;
- if (numerator > denominator) {
- a = numerator;
- b = denominator;
- } else {
- a = denominator;
- b = numerator;
- }
- while (b != 0) {
- int r = b;
- b = a % b;
- a = r;
- }
-
- return a;
+ u32 a, b;
+
+ if (!numerator || !denominator)
+ return 0;
+ if (numerator > denominator) {
+ a = numerator;
+ b = denominator;
+ } else {
+ a = denominator;
+ b = numerator;
+ }
+ while (b != 0) {
+ int r = b;
+
+ b = a % b;
+ a = r;
+ }
+
+ return a;
}
-/* FIXME: calc using u64 */
static int pll_clk_get_best_set(unsigned long fin_hz, unsigned long fout_hz,
u32 *best_nr, u32 *best_nf, u32 *best_no)
{
- u32 nr, nf, no, nonr;
- u32 nr_out, nf_out, no_out;
- u32 n;
- u32 YFfenzi;
- u32 YFfenmu;
- u64 fref, fvco, fout;
- u32 gcd_val = 0;
-
-
- nr_out = PLL_NR_MAX + 1;
- no_out = 0;
-
-// printk("pll_clk_get_set fin=%lu,fout=%lu\n", fin_hz, fout_hz);
- if(!fin_hz || !fout_hz || fout_hz == fin_hz)
- return -EINVAL;
- gcd_val = clk_gcd(fin_hz, fout_hz);
-
-// printk("gcd_val = %d\n",gcd_val);
-
- YFfenzi = fout_hz / gcd_val;
- YFfenmu = fin_hz / gcd_val;
-
-// printk("YFfenzi = %d, YFfenmu = %d\n",YFfenzi,YFfenmu);
-
- for(n = 1;; n++) {
- nf = YFfenzi * n;
- nonr = YFfenmu * n;
- if(nf > PLL_NF_MAX || nonr > (PLL_NO_MAX * PLL_NR_MAX))
- break;
- for(no = 1; no <= PLL_NO_MAX; no++) {
- if(!(no == 1 || !(no % 2)))
- continue;
-
- if(nonr % no)
- continue;
- nr = nonr / no;
-
- if(nr > PLL_NR_MAX) //PLL_NR_MAX
- continue;
-
- fref = fin_hz / nr;
- if(fref < PLL_FREF_MIN || fref > PLL_FREF_MAX)
- continue;
-
- fvco = fref * nf;
- if(fvco < PLL_FVCO_MIN || fvco > PLL_FVCO_MAX)
- continue;
- fout = fvco / no;
- if(fout < PLL_FOUT_MIN || fout > PLL_FOUT_MAX)
- continue;
-
- /* output all available PLL settings */
- //printk("nr=%d,\tnf=%d,\tno=%d\n",nr,nf,no);
- //printk("_PLL_SET_CLKS(%lu,\t%d,\t%d,\t%d),\n",fout_hz/KHZ,nr,nf,no);
-
- /* select the best from all available PLL settings */
- if((nr < nr_out) || ((nr == nr_out)&&(no > no_out)))
- {
- nr_out = nr;
- nf_out = nf;
- no_out = no;
- }
- }
-
- }
-
- /* output the best PLL setting */
- if((nr_out <= PLL_NR_MAX) && (no_out > 0)){
- //printk("_PLL_SET_CLKS(%lu,\t%d,\t%d,\t%d),\n",fout_hz/KHZ,nr_out,nf_out,no_out);
- if(best_nr && best_nf && best_no){
+ u32 nr, nf, no, nonr;
+ u32 nr_out, nf_out, no_out;
+ u32 n;
+ u32 YFfenzi;
+ u32 YFfenmu;
+ u64 fref, fvco, fout;
+ u32 gcd_val = 0;
+
+ nr_out = PLL_NR_MAX + 1;
+ no_out = 0;
+
+ if (!fin_hz || !fout_hz || fout_hz == fin_hz)
+ return -EINVAL;
+ gcd_val = clk_gcd(fin_hz, fout_hz);
+
+ YFfenzi = fout_hz / gcd_val;
+ YFfenmu = fin_hz / gcd_val;
+
+ for (n = 1;; n++) {
+ nf = YFfenzi * n;
+ nonr = YFfenmu * n;
+ if (nf > PLL_NF_MAX || nonr > (PLL_NO_MAX * PLL_NR_MAX))
+ break;
+
+ for (no = 1; no <= PLL_NO_MAX; no++) {
+ if (!(no == 1 || !(no % 2)))
+ continue;
+
+ if (nonr % no)
+ continue;
+ nr = nonr / no;
+
+ if (nr > PLL_NR_MAX)
+ continue;
+
+ fref = fin_hz / nr;
+ if (fref < PLL_FREF_MIN || fref > PLL_FREF_MAX)
+ continue;
+
+ fvco = fref * nf;
+ if (fvco < PLL_FVCO_MIN || fvco > PLL_FVCO_MAX)
+ continue;
+
+ fout = fvco / no;
+ if (fout < PLL_FOUT_MIN || fout > PLL_FOUT_MAX)
+ continue;
+
+ /* select the best from all available PLL settings */
+ if ((no > no_out) || ((no == no_out) && (nr < nr_out))) {
+ nr_out = nr;
+ nf_out = nf;
+ no_out = no;
+ }
+ }
+ }
+
+ /* output the best PLL setting */
+ if ((nr_out <= PLL_NR_MAX) && (no_out > 0)) {
+ if (best_nr && best_nf && best_no) {
*best_nr = nr_out;
*best_nf = nf_out;
*best_no = no_out;
config ROCK_CHIP_SOC_CAMERA
tristate "rockchip supported soc cameras "
- select SOC_CAMERA
- select VIDEOBUF_DMA_CONTIG
default y
menu "rockchip camera sensor interface driver"
config RK30_CAMERA_ONEFRAME
tristate "rk30_camera_oneframe"
depends on ROCKCHIP_CAMERA_SENSOR_INTERFACE
- default y
+ select SOC_CAMERA
+ select VIDEOBUF_DMA_CONTIG
+ default n
config RK30_CAMERA_PINGPONG
tristate "rk30_camera_pingpong"
depends on ROCKCHIP_CAMERA_SENSOR_INTERFACE
-
+ select SOC_CAMERA
+ select VIDEOBUF_DMA_CONTIG
+ default n
endmenu
extern struct dwc_otg_platform_data usb20otg_pdata_rk3126;
extern struct dwc_otg_platform_data usb20host_pdata_rk3126;
extern struct dwc_otg_platform_data usb20ohci_pdata_rk3126;
+extern struct rkehci_platform_data usb20ehci_pdata_rk3126;
struct dwc_otg_platform_data {
void *privdata;
};
#endif
-#ifdef CONFIG_USB20_HOST
+#if defined(CONFIG_USB20_HOST) || defined(CONFIG_USB_EHCI_RK)
static void usb20host_hw_init(void)
{
/* Turn off differential receiver in suspend mode */
};
#endif
+#ifdef CONFIG_USB_EHCI_RK
+static void usb20ehci_phy_suspend(void *pdata, int suspend)
+{
+ struct rkehci_platform_data *usbpdata = pdata;
+
+ if (suspend) {
+ /* enable soft control */
+ writel(UOC_HIWORD_UPDATE(0x1d5, 0x1ff, 0),
+ RK_GRF_VIRT + RK312X_GRF_UOC1_CON5);
+ usbpdata->phy_status = 1;
+ } else {
+ /* exit suspend */
+ writel(UOC_HIWORD_UPDATE(0x0, 0x1, 0),
+ RK_GRF_VIRT + RK312X_GRF_UOC1_CON5);
+ usbpdata->phy_status = 0;
+ }
+}
+
+static void usb20ehci_soft_reset(void *pdata, enum rkusb_rst_flag rst_type)
+{
+ struct rkehci_platform_data *usbpdata = pdata;
+ struct reset_control *rst_host_h, *rst_host_p, *rst_host_c;
+
+ rst_host_h = devm_reset_control_get(usbpdata->dev, "host_ahb");
+ rst_host_p = devm_reset_control_get(usbpdata->dev, "host_phy");
+ rst_host_c = devm_reset_control_get(usbpdata->dev, "host_controller");
+ if (IS_ERR(rst_host_h) || IS_ERR(rst_host_p) || IS_ERR(rst_host_c)) {
+ dev_err(usbpdata->dev, "Fail to get reset control from dts\n");
+ return;
+ }
+
+ switch(rst_type) {
+ case RST_POR:
+ /* PHY reset */
+ writel(UOC_HIWORD_UPDATE(0x1, 0x3, 0),
+ RK_GRF_VIRT + RK312X_GRF_UOC1_CON5);
+ reset_control_assert(rst_host_p);
+ udelay(15);
+ writel(UOC_HIWORD_UPDATE(0x2, 0x3, 0),
+ RK_GRF_VIRT + RK312X_GRF_UOC1_CON5);
+
+ udelay(1500);
+ reset_control_deassert(rst_host_p);
+
+ /* Controller reset */
+ reset_control_assert(rst_host_c);
+ reset_control_assert(rst_host_h);
+
+ udelay(5);
+
+ reset_control_deassert(rst_host_c);
+ reset_control_deassert(rst_host_h);
+ break;
+
+ default:
+ break;
+ }
+}
+
+static void usb20ehci_clock_init(void *pdata)
+{
+ struct rkehci_platform_data *usbpdata = pdata;
+ struct clk *ahbclk, *phyclk;
+
+ if (soc_is_rk3126b())
+ ahbclk = devm_clk_get(usbpdata->dev, "hclk_hoct0_3126b");
+ else
+ ahbclk = devm_clk_get(usbpdata->dev, "hclk_hoct0_3126");
+ if (IS_ERR(ahbclk)) {
+ dev_err(usbpdata->dev, "Failed to get hclk_usb1\n");
+ return;
+ }
+
+ phyclk = devm_clk_get(usbpdata->dev, "clk_usbphy1");
+ if (IS_ERR(phyclk)) {
+ dev_err(usbpdata->dev, "Failed to get clk_usbphy1\n");
+ return;
+ }
+
+ usbpdata->phyclk = phyclk;
+ usbpdata->ahbclk = ahbclk;
+}
+
+static void usb20ehci_clock_enable(void *pdata, int enable)
+{
+ struct rkehci_platform_data *usbpdata = pdata;
+
+ if (enable) {
+ clk_prepare_enable(usbpdata->ahbclk);
+ clk_prepare_enable(usbpdata->phyclk);
+ } else {
+ clk_disable_unprepare(usbpdata->ahbclk);
+ clk_disable_unprepare(usbpdata->phyclk);
+ }
+}
+
+struct rkehci_platform_data usb20ehci_pdata_rk3126 = {
+ .phyclk = NULL,
+ .ahbclk = NULL,
+ .phy_status = 0,
+ .hw_init = usb20host_hw_init,
+ .phy_suspend = usb20ehci_phy_suspend,
+ .soft_reset = usb20ehci_soft_reset,
+ .clock_init = usb20ehci_clock_init,
+ .clock_enable = usb20ehci_clock_enable,
+ .get_status = usb20host_get_status,
+};
+#endif
+
struct dwc_otg_platform_data usb20ohci_pdata_rk3126;
#ifdef CONFIG_OF
t2 |= PORT_WKOC_E | PORT_WKCONN_E;
}
-#ifdef CONFIG_USB_EHCI_RK
- /* RK3288 do not support OHCI controller, so clear PORT_OWNER
- * here, otherwise EHCI can't be used anymore. wlf@20140325 */
- t2 &= ~PORT_OWNER;
-#endif
-
if (t1 != t2) {
ehci_vdbg (ehci, "port %d, %08x -> %08x\n",
port + 1, t1, t2);
ehci_dbg (ehci,
"port %d low speed --> companion\n",
wIndex + 1);
-#ifdef CONFIG_USB_EHCI_RK
- /* RK3288 do not support OHCI controller, so can't set PORT_OWNER
- * here, otherwise EHCI can't be used anymore. wlf@20140325 */
- retval = -ENODEV;
- break;
-#endif
temp |= PORT_OWNER;
} else {
ehci_vdbg (ehci, "port %d reset\n", wIndex + 1);
}
EHCI_PRINT("%s, disable host controller\n", __func__);
- usb_remove_hcd(hcd);
- /* reset cru and reinitialize EHCI controller */
- pldata->soft_reset(pldata, RST_RECNT);
- usb_add_hcd(hcd, hcd->irq, IRQF_DISABLED | IRQF_SHARED);
if (pldata->phy_suspend)
pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
/* do not disable EHCI clk, otherwise RK3288
.compatible = "rockchip,rk3288_rk_ehci_host",
.data = &rkehci_pdata_rk3288,
},
+ {
+ .compatible = "rockchip,rk3126_ehci",
+ .data = &usb20ehci_pdata_rk3126,
+ },
{},
};
.extra_priv_size = sizeof(struct rk_ehci_hcd),
};
+static void rk32_ehci_relinquish_port(struct usb_hcd *hcd, int portnum)
+{
+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+ u32 *status_reg = &ehci->regs->port_status[--portnum];
+ u32 portsc;
+
+ portsc = ehci_readl(ehci, status_reg);
+ portsc &= ~(PORT_OWNER | PORT_RWC_BITS);
+
+ ehci_writel(ehci, portsc, status_reg);
+}
+
static int __init ehci_rk_init(void)
{
if (usb_disabled())
return -ENODEV;
ehci_init_driver(&rk_ehci_hc_driver, &rk_overrides);
+
+ /*
+ * Work-around: RK3288 do not support OHCI controller, so our
+ * vendor-spec ehci driver has to prevent handing off this port to
+ * OHCI by standard ehci-hub driver, put PORT_OWNER back to 0 manually.
+ */
+ if (cpu_is_rk3288())
+ rk_ehci_hc_driver.relinquish_port = rk32_ehci_relinquish_port;
+
return platform_driver_register(&rk_ehci_driver);
}
+
module_init(ehci_rk_init);
static void __exit ehci_rk_cleanup(void)
memcpy(&header, src, sizeof(header));
src += sizeof(header);
+
+ if (header.type != 0x4d42) {
+ pr_err("not bmp file type[%x], can't support\n", header.type);
+ return -1;
+ }
memcpy(&infoheader, src, sizeof(infoheader));
*width = infoheader.width;
*height = infoheader.height;
#include <linux/kthread.h>
#include <linux/fb.h>
#include <linux/init.h>
+#include <linux/vmalloc.h>
#include <asm/div64.h>
#include <linux/uaccess.h>
#include <linux/rk_fb.h>
EXPORT_SYMBOL(video_data_to_mirroring);
#endif
-static uint32_t kernel_logo_addr;
-static int __init kernel_logo_setup(char *str)
-{
- if(str) {
- sscanf(str, "%x", &kernel_logo_addr);
- }
-
- return 0;
-}
-early_param("kernel_logo", kernel_logo_setup);
+extern phys_addr_t uboot_logo_base;
+extern phys_addr_t uboot_logo_size;
+extern phys_addr_t uboot_logo_offset;
static struct rk_fb_trsm_ops *trsm_lvds_ops;
static struct rk_fb_trsm_ops *trsm_edp_ops;
static struct rk_fb_trsm_ops *trsm_mipi_ops;
fb_id = 3;
else if (!strcmp(id, "fb4") && (dev_drv->lcdc_win_num > 4))
fb_id = 4;
- else
- dev_err(dev_drv->dev, "get_extend_fb_id info error\n");
return fb_id;
}
dev_drv->ops->dsp_black(dev_drv, 1);
if (dev_drv->ops->set_screen_scaler)
dev_drv->ops->set_screen_scaler(dev_drv, dev_drv->screen0, 0);
- } else if ((rk_fb->disp_mode == NO_DUAL) && (enable)) {
- if (dev_drv->ops->dsp_black)
- dev_drv->ops->dsp_black(dev_drv, 1);
}
if (!enable) {
return 0;
/* if used one lcdc to dual disp, no need to close win */
- if ((rk_fb->disp_mode == ONE_DUAL) ||
- (rk_fb->disp_mode == NO_DUAL)) {
+ if (rk_fb->disp_mode == ONE_DUAL) {
dev_drv->cur_screen = dev_drv->screen0;
dev_drv->ops->load_screen(dev_drv, 1);
info->var.activate |= FB_ACTIVATE_FORCE;
if (rk_fb->disp_mode == DUAL) {
rk_fb_update_ext_info(info, pmy_info, 1);
- } else if ((rk_fb->disp_mode == ONE_DUAL) ||
- (rk_fb->disp_mode == NO_DUAL)) {
+ } else if (rk_fb->disp_mode == ONE_DUAL) {
info->var.grayscale &= 0xff;
info->var.grayscale |=
(dev_drv->cur_screen->xsize << 8) +
rk_fb_alloc_buffer(main_fbi, 0); /* only alloc memory for main fb */
dev_drv->uboot_logo = support_uboot_display();
- if (kernel_logo_addr) {
+ if (uboot_logo_offset && uboot_logo_base) {
struct rk_lcdc_win *win = dev_drv->win[0];
- char *addr = phys_to_virt(kernel_logo_addr);
int width, height, bits;
+ phys_addr_t start = uboot_logo_base + uboot_logo_offset;
+ unsigned int size = uboot_logo_size - uboot_logo_offset;
+ unsigned int nr_pages;
+ struct page **pages;
+ char *vaddr;
+ int i = 0;
+
+ nr_pages = size >> PAGE_SHIFT;
+ pages = kzalloc(sizeof(struct page) * nr_pages,
+ GFP_KERNEL);
+ while (i < nr_pages) {
+ pages[i] = phys_to_page(start);
+ start += PAGE_SIZE;
+ i++;
+ }
+ vaddr = vmap(pages, nr_pages, VM_MAP,
+ pgprot_writecombine(PAGE_KERNEL));
+ if (!vaddr) {
+ pr_err("failed to vmap phy addr %x\n",
+ uboot_logo_base + uboot_logo_offset);
+ return -1;
+ }
+
+ if(bmpdecoder(vaddr, main_fbi->screen_base, &width,
+ &height, &bits)) {
+ kfree(pages);
+ vunmap(vaddr);
+ return 0;
+ }
+ kfree(pages);
+ vunmap(vaddr);
+ if (width > main_fbi->var.xres ||
+ height > main_fbi->var.yres) {
+ pr_err("ERROR: logo size out of screen range");
+ return 0;
+ }
- bmpdecoder(addr, main_fbi->screen_base,
- &width, &height, &bits);
win->area[0].format = rk_fb_data_fmt(0, bits);
win->area[0].y_vir_stride = width * bits >> 5;
win->area[0].xpos = (main_fbi->var.xres - width) >> 1;
- win->area[0].ypos = (main_fbi->var.yres - height) >> 1;;
+ win->area[0].ypos = (main_fbi->var.yres - height) >> 1;
win->area[0].xsize = width;
win->area[0].ysize = height;
win->area[0].xact = width;
void __init rockchip_efuse_init(void);
void __init rockchip_suspend_init(void);
void __init rockchip_ion_reserve(void);
+void __init rockchip_uboot_mem_reserve(void);
enum rockchip_pm_policy {
ROCKCHIP_PM_POLICY_PERFORMANCE = 0,
projects / firefly-linux-kernel-4.4.55.git / commitdiff
