arm64: dts: rockchip: rk3328: Fix the saradc compitiable
authorDavid Wu <david.wu@rock-chips.com>
Fri, 10 Mar 2017 09:09:27 +0000 (17:09 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Mon, 13 Mar 2017 04:45:22 +0000 (12:45 +0800)
The rk3328 saradc is the same as rk3399, so change the compitiable,
they are both 6 channels.

Change-Id: Ia6104e8c5c3590cc745792b8cd3a457a15bb53d2
Signed-off-by: David Wu <david.wu@rock-chips.com>
Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
arch/arm64/boot/dts/rockchip/rk3328.dtsi

index 205593f56fe759706ea6fd321c08e66059ebd489..f81bc20e69ee93f63d2a4b3d50ec63d053936714 100644 (file)
@@ -5,6 +5,7 @@ Required properties:
    - "rockchip,saradc": for rk3188, rk3288
    - "rockchip,rk3066-tsadc": for rk3036
    - "rockchip,rk3399-saradc": for rk3399
+   - "rockchip,rk3328-saradc", "rockchip,rk3399-saradc": for rk3328
 
 - reg: physical base address of the controller and length of memory mapped
        region.
index 077fcf772015a994661cab77cf5b9f3164f7ff8f..437b38b0ef62395f1693019902dab9eeada4d73d 100644 (file)
        };
 
        saradc: saradc@ff280000 {
-               compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
+               compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
                reg = <0x0 0xff280000 0x0 0x100>;
                interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
                #io-channel-cells = <1>;