UPSTREAM: usb: dwc2: Add functions to check the HW OTG config

Added functions to query the GHWCFG2.OTG_MODE. This tells us whether the
controller hardware is configured for OTG, device-only, or host-only.

Change-Id: I8f927d130a675ceb598b118d0c9a4e5d5b698739
Signed-off-by: John Youn <johnyoun@synopsys.com>
Tested-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 6bea962053e76a4407f0d138184a8737eea960ee)

diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
index 15f359fe76d3b67cc0ca920e5e966a74fc0bc7e5..b700a47e026a6e406b1a2ff6e635ea42d7c4f4c4 100644 (file)
--- a/drivers/usb/dwc2/core.c
+++ b/drivers/usb/dwc2/core.c
@@ -3342,6 +3342,43 @@ void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
        dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
 }
 
+/* Returns the controller's GHWCFG2.OTG_MODE. */
+unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg)
+{
+       u32 ghwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
+
+       return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>
+               GHWCFG2_OP_MODE_SHIFT;
+}
+
+/* Returns true if the controller is capable of DRD. */
+bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
+{
+       unsigned op_mode = dwc2_op_mode(hsotg);
+
+       return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) ||
+               (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) ||
+               (op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE);
+}
+
+/* Returns true if the controller is host-only. */
+bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
+{
+       unsigned op_mode = dwc2_op_mode(hsotg);
+
+       return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
+               (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
+}
+
+/* Returns true if the controller is device-only. */
+bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg)
+{
+       unsigned op_mode = dwc2_op_mode(hsotg);
+
+       return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
+               (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE);
+}
+
 MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
 MODULE_AUTHOR("Synopsys, Inc.");
 MODULE_LICENSE("Dual BSD/GPL");

diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index d605d7c88cdf288416da41358baea26cc00d873a..6f5c6afe77caa2526e0f0994927de407a428e0d1 100644 (file)
--- a/drivers/usb/dwc2/core.h
+++ b/drivers/usb/dwc2/core.h
@@ -1165,6 +1165,19 @@ extern int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
 extern int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
 extern int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
 
+/*
+ * The following functions check the controller's OTG operation mode
+ * capability (GHWCFG2.OTG_MODE).
+ *
+ * These functions can be used before the internal hsotg->hw_params
+ * are read in and cached so they always read directly from the
+ * GHWCFG2 register.
+ */
+unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg);
+bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
+bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
+bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
+
 /*
  * Dump core registers and SPRAM
  */