clk_disable_unprepare(dsi->phy.refclk);
clk_disable_unprepare(dsi->dsi_pclk);
clk_disable_unprepare(dsi->dsi_host_pclk);
+
if (dsi->ops.id == DWC_DSI_VERSION_RK312x) {
clk_disable_unprepare(dsi->h2p_hclk);
clk_disable_unprepare(dsi->dsi_pd);
static int rk32_dsi_enable(void)
{
MIPI_DBG("rk32_dsi_enable-------\n");
- rk_fb_get_prmry_screen(dsi0->screen.screen);
- dsi0->screen.lcdc_id = dsi0->screen.screen->lcdc_id;
- rk32_init_phy_mode(dsi0->screen.lcdc_id);
+ if (!dsi0->clk_on) {
+ dsi0->clk_on = 1;
+ rk_fb_get_prmry_screen(dsi0->screen.screen);
+ dsi0->screen.lcdc_id = dsi0->screen.screen->lcdc_id;
+ rk32_init_phy_mode(dsi0->screen.lcdc_id);
- dsi_init(0, 0);
- if (rk_mipi_get_dsi_num() == 2)
- dsi_init(1, 0);
+ dsi_init(0, 0);
+ if (rk_mipi_get_dsi_num() == 2)
+ dsi_init(1, 0);
- rk_mipi_screen_standby(0);
+ rk_mipi_screen_standby(0);
- /*
- After the core reset, DPI waits for the first VSYNC active transition to start signal sampling, including
- pixel data, and preventing image transmission in the middle of a frame.
+ /* After the core reset, DPI waits for the first VSYNC
+ active transition to start signal sampling, including pixel data,
+ and preventing image transmission in the middle of a frame.
*/
- dsi_is_enable(0, 0);
- if (rk_mipi_get_dsi_num() == 2)
- dsi_is_enable(1, 0);
+ dsi_is_enable(0, 0);
+ if (rk_mipi_get_dsi_num() == 2)
+ dsi_is_enable(1, 0);
- dsi_enable_video_mode(0, 1);
- if (rk_mipi_get_dsi_num() == 2)
- dsi_enable_video_mode(1, 1);
+ dsi_enable_video_mode(0, 1);
+ if (rk_mipi_get_dsi_num() == 2)
+ dsi_enable_video_mode(1, 1);
- dsi_is_enable(0, 1);
- if (rk_mipi_get_dsi_num() == 2)
- dsi_is_enable(1, 1);
+ dsi_is_enable(0, 1);
+ if (rk_mipi_get_dsi_num() == 2)
+ dsi_is_enable(1, 1);
+ }
return 0;
}
static int rk32_dsi_disable(void)
{
MIPI_DBG("rk32_dsi_disable-------\n");
- rk_mipi_screen_standby(1);
- dsi_power_off(0);
- if (rk_mipi_get_dsi_num() == 2)
- dsi_power_off(1);
+ if (dsi0->clk_on) {
+ dsi0->clk_on = 0;
+ rk_mipi_screen_standby(1);
+ dsi_power_off(0);
+ if (rk_mipi_get_dsi_num() == 2)
+ dsi_power_off(1);
+ }
return 0;
}
if (dsi->ops.id == DWC_DSI_VERSION_RK312x) {
clk_prepare_enable(dsi->dsi_host_pclk);
clk_prepare_enable(dsi->h2p_hclk);
- }
+ } else if (dsi->ops.id == DWC_DSI_VERSION_RK3368)
+ clk_prepare_enable(dsi->dsi_host_pclk);
+
clk_prepare_enable(dsi->dsi_pd);
udelay(10);
}
+
dev_info(&pdev->dev, "rk mipi_dsi probe success!\n");
dev_info(&pdev->dev, "%s\n", RK_MIPI_DSI_VERSION_AND_TIME);