#define RKPM_BOOTRAM_BASE (RK312X_IMEM_VIRT)
#define RKPM_BOOTRAM_SIZE (RK312X_IMEM_SIZE)
-/*sys resume code in boot ram*/
+#define RKPM_BOOT_CODE_OFFSET (0x0)
+#define RK312XPM_BOOT_CODE_SIZE (0x700)
+
+#define RK312XPM_BOOT_DATA_OFFSET (RKPM_BOOT_CODE_OFFSET \
+ + RK312XPM_BOOT_CODE_SIZE)
+#define RKPM_BOOT_DATA_SIZE (RKPM_BOOTDATA_ARR_SIZE*4)
+
+#define RK312XPM_BOOT_DDRCODE_OFFSET (RK312XPM_BOOT_DATA_OFFSET\
+ +RKPM_BOOT_DATA_SIZE)
+
#define RKPM_BOOT_CODE_PHY (RKPM_BOOTRAM_PHYS + RKPM_BOOT_CODE_OFFSET)
#define RKPM_BOOT_CODE_BASE (RKPM_BOOTRAM_BASE + RKPM_BOOT_CODE_OFFSET)
-
-/*sys resume data in boot ram*/
-#define RKPM_BOOT_DATA_PHY (RKPM_BOOTRAM_PHYS + RKPM_BOOT_DATA_OFFSET)
-#define RKPM_BOOT_DATA_BASE (RKPM_BOOTRAM_BASE + RKPM_BOOT_DATA_OFFSET)
+#define RKPM_BOOT_DATA_PHY (RKPM_BOOTRAM_PHYS + RK312XPM_BOOT_DATA_OFFSET)
+#define RKPM_BOOT_DATA_BASE (RKPM_BOOTRAM_BASE + RK312XPM_BOOT_DATA_OFFSET)
/*ddr resume data in boot ram*/
-#define RKPM_BOOT_DDRCODE_PHY (RKPM_BOOTRAM_PHYS + RKPM_BOOT_DDRCODE_OFFSET)
-#define RKPM_BOOT_DDRCODE_BASE (RKPM_BOOTRAM_BASE + RKPM_BOOT_DDRCODE_OFFSET)
+#define RKPM_BOOT_DDRCODE_PHY (RKPM_BOOTRAM_PHYS \
+ + RK312XPM_BOOT_DDRCODE_OFFSET)
+#define RKPM_BOOT_DDRCODE_BASE (RKPM_BOOTRAM_BASE \
+ + RK312XPM_BOOT_DDRCODE_OFFSET)
+
/*#define RKPM_BOOT_CPUSP_PHY (RKPM_BOOTRAM_PHYS+((RKPM_BOOTRAM_SIZE-1)&~0x7))*/
#define RKPM_BOOT_CPUSP_PHY (0x00 + ((RKPM_BOOTRAM_SIZE - 1) & (~(0x7))))
#define RKPM_BOOT_CODE_BASE (RKPM_BOOTRAM_BASE + PM_BOOT_CODE_OFFSET)
#define RKPM_BOOT_CODE_SIZE (0x100)
**************************************************/
-extern void rkpm_slp_cpu_resume(void);
+extern void rk312x_pm_slp_cpu_resume(void);
static void sram_data_for_sleep(char *boot_save, char *int_save, u32 flag)
{
memcpy(boot_save, addr_base, sr_size);
/**********move resume code and data to boot sram*************/
data_dst = (char *)RKPM_BOOT_CODE_BASE;
- data_src = (char *)rkpm_slp_cpu_resume;
- data_size = RKPM_BOOT_CODE_SIZE;
+ data_src = (char *)rk312x_pm_slp_cpu_resume;
+ data_size = RK312XPM_BOOT_CODE_SIZE;
memcpy(data_dst, data_src, data_size);
data_dst = (char *)resume_data_base;
/*grf_writel(0X00030002, 0xb4);
rk3126 GPIO1A1 : RK3128 GPIO3C1 iomux pmic-sleep*/
- if ((pmic_sleep_gpio == 0) || (pmic_sleep_gpio == 0x1a10)) {
+ if (pmic_sleep_gpio == 0x1a10) {
+ ddr_printch('a');
gpio_pmic_sleep_mode = grf_readl(0xb8);
grf_writel(0X000C000C, 0xb8);
}
/*rk3126 GPIO1A1 : RK3128 GPIO3C1 iomux pmic-sleep*/
if (pmic_sleep_gpio == 0x3c10) {
- ddr_printch('a');
+ ddr_printch('c');
gpio_pmic_sleep_mode = grf_readl(0xe0);
grf_writel(0X000C0008, 0xe0);
}
} else if (rkpm_chk_val_ctrbits(ctrbits, RKPM_CTR_ARMOFF_LPMD)) {
rkpm_ddr_printascii("-armoff-");
/*arm power off */
+ pwr_mode_config |= 0
+ |BIT(pmu_clk_core_src_gate_en)
+ |BIT(pmu_clk_bus_src_gate_en)
+ | BIT(pmu_core_pd_en)
+ /* | BIT(pmu_use_if)//aaa*/
+ /* | BIT(pmu_sref_enter_en)*/
+ |BIT(pmu_int_en)
+ /* | BIT(pmu_wait_osc_24m)*/
+ /* | BIT(pmu_ddr_gating_en)*/
+ /* | BIT(pmu_ddr0io_ret_de_req)*/
+ | BIT(pmu_clr_core)
+ /* | BIT(pmu_clr_crypto)*/
+ /* | BIT(pmu_clr_sys)*/
+ /*| BIT(pmu_clr_vio)*/
+ /*| BIT(pmu_clr_video)*/
+ /*| BIT(pmu_clr_peri)*/
+ /* | BIT(pmu_clr_msch)*/
+ /*| BIT(pmu_clr_gpu) */
+ ;
+ } else if (rkpm_chk_val_ctrbits(ctrbits, RKPM_CTR_ARMOFF_LPMD)) {
+ rkpm_ddr_printascii("-armoff ddr -");
+ /*arm power off */
pwr_mode_config |= 0
|BIT(pmu_clk_core_src_gate_en)
|BIT(pmu_clk_bus_src_gate_en)
;
}
pmu_writel(32 * 30, RK312X_PMU_OSC_CNT);
+ pmu_writel(0xbb80, RK312X_PMU_CORE_PWRUP_CNT);
pmu_writel(pwr_mode_config, RK312X_PMU_PWRMODE_CON);
rk312x_powermode = pwr_mode_config;
return pmu_readl(RK312X_PMU_PWRMODE_CON);
static void sram_code_data_save(u32 pwrmode)
{
sleep_resume_data[RKPM_BOOTDATA_L2LTY_F] = 0;
- sleep_resume_data[RKPM_BOOTDATA_ARM_ERRATA_818325_F] = 0;
+ if (rkpm_chk_ctrbits(RKPM_CTR_VOL_PWM0))
+ sleep_resume_data[RKPM_BOOTDATA_ARM_ERRATA_818325_F] |= 0x01;
+ if (rkpm_chk_ctrbits(RKPM_CTR_VOL_PWM1))
+ sleep_resume_data[RKPM_BOOTDATA_ARM_ERRATA_818325_F] |= 0x02;
+ if (rkpm_chk_ctrbits(RKPM_CTR_VOL_PWM2))
+ sleep_resume_data[RKPM_BOOTDATA_ARM_ERRATA_818325_F] |= 0x04;
sleep_resume_data[RKPM_BOOTDATA_DDR_F] = 0;
sleep_resume_data[RKPM_BOOTDATA_CPUSP] = RKPM_BOOT_CPUSP_PHY;
/*in sys resume ,ddr is need resume*/
{
slp312x_uartdbg_resume();
}
+extern void rk_sram_suspend(void);
static void rkpm_slp_setting(void)
{
rk_usb_power_down();
+ rk_sram_suspend();
}
static void rkpm_save_setting_resume_first(void)
{
void PIE_FUNC(ddr_suspend)(void);
void PIE_FUNC(ddr_resume)(void);
-static __sramdata u32 rkpm_pwm_duty0;
-static __sramdata u32 rkpm_pwm_duty1;
-static __sramdata u32 rkpm_pwm_duty2;
#define PWM_VOLTAGE 0x600
void PIE_FUNC(pwm_regulator_suspend)(void)
{
+ int gpio0_inout;
+ int gpio0_ddr;
+
+ cru_writel(0x1e000000, 0xf0);
+
if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM0)) {
- rkpm_pwm_duty0 = readl_relaxed(RK_PWM_VIRT + 0x08);
- writel_relaxed(PWM_VOLTAGE, RK_PWM_VIRT + 0x08);
+ grf_writel(0x00100000, 0xb4);/*iomux gpio0d2*/
+ gpio0_inout = readl_relaxed(RK_GPIO_VIRT(0) + 0x04);
+ gpio0_ddr = readl_relaxed(RK_GPIO_VIRT(0));
+ writel_relaxed(gpio0_inout | 0x04000000
+ , RK_GPIO_VIRT(0) + 0x04);
+ dsb();
+ writel_relaxed(gpio0_ddr | 0x04000000, RK_GPIO_VIRT(0));
}
if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM1)) {
- rkpm_pwm_duty1 = readl_relaxed(RK_PWM_VIRT + 0x18);
- writel_relaxed(PWM_VOLTAGE, RK_PWM_VIRT + 0x18);
+ grf_writel(0x00400000, 0xb4);/*iomux gpio0d3*/
+ gpio0_inout = readl_relaxed(RK_GPIO_VIRT(0) + 0x04);
+ gpio0_ddr = readl_relaxed(RK_GPIO_VIRT(0));
+ writel_relaxed(gpio0_inout | 0x08000000
+ , RK_GPIO_VIRT(0) + 0x04);
+ dsb();
+ writel_relaxed(gpio0_ddr | 0x08000000, RK_GPIO_VIRT(0));
}
if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM2)) {
- rkpm_pwm_duty2 = readl_relaxed(RK_PWM_VIRT + 0x28);
- writel_relaxed(PWM_VOLTAGE, RK_PWM_VIRT + 0x28);
+ grf_writel(0x01000000, 0xb4);/*iomux gpio0d4*/
+ gpio0_inout = readl_relaxed(RK_GPIO_VIRT(0) + 0x04);
+ gpio0_ddr = readl_relaxed(RK_GPIO_VIRT(0));
+ writel_relaxed(gpio0_inout | 0x10000000
+ , RK_GPIO_VIRT(0) + 0x04);
+ dsb();
+ writel_relaxed(gpio0_ddr | 0x10000000, RK_GPIO_VIRT(0));
}
- rkpm_udelay(30);
+
}
void PIE_FUNC(pwm_regulator_resume)(void)
{
- rkpm_udelay(30);
- if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM0))
- writel_relaxed(rkpm_pwm_duty0, RK_PWM_VIRT + 0x08);
-
- if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM1))
- writel_relaxed(rkpm_pwm_duty1, RK_PWM_VIRT + 0x18);
- if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM2))
- writel_relaxed(rkpm_pwm_duty2, RK_PWM_VIRT + 0x28);
- rkpm_udelay(30);
}
+
static void reg_pread(void)
{
int i;
n = readl_relaxed(RK_PMU_VIRT);
n = readl_relaxed(RK_PWM_VIRT);
}
+void PIE_FUNC(msch_bus_idle_request)(void)
+{
+ u32 val;
+ rkpm_sram_printch('6');
+ val = pmu_readl(RK312X_PMU_IDLE_REQ);
+ val |= 0x40;
+ pmu_writel(val, RK312X_PMU_IDLE_REQ);
+ dsb();
+ while (((pmu_readl(RK312X_PMU_IDLE_ST) & 0x00400040) != 0x00400040))
+ ;
+}
static void __init rk312x_suspend_init(void)
{
struct device_node *parent;
rkpm_set_sram_ops_ddr(fn_to_pie(rockchip_pie_chunk
, &FUNC(ddr_suspend))
, fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_resume)));
+ rkpm_set_sram_ops_bus(fn_to_pie(rockchip_pie_chunk
+ , &FUNC(msch_bus_idle_request)));
rkpm_set_sram_ops_volt(fn_to_pie(rockchip_pie_chunk
, &FUNC(pwm_regulator_suspend))
, fn_to_pie(rockchip_pie_chunk, &FUNC(pwm_regulator_resume)));
--- /dev/null
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/memory.h>
+
+#define _RKPM_SEELP_S_INCLUDE_
+#include "pm.h"
+
+.text
+ENTRY(rk312x_pm_slp_cpu_while_tst)
+stmfd sp!, { r3 - r12, lr }
+
+1: mov r3,r3
+ b 1b
+
+ldmfd sp!, { r3 - r12, pc }
+
+.data
+.align
+ENTRY(rk312x_pm_slp_cpu_resume)
+9: mov r1,r1
+
+#if 0
+ ldr r4, = 0x20068000
+ mov r5, #67
+ str r5,[r4]
+#endif
+ setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set SVC, irqs off
+
+ MRC p15,0,R1,c0,c0,5
+ AND R1,R1,#0xf
+ CMP R1,#0
+ BEQ cpu0Run
+
+cpu1loop:
+ mov r3, #50
+ //str r3,[r4]
+ WFENE // ; wait if it.s locked
+ B cpu1loop // ; if any failure, loop
+
+cpu0Run:
+ 1: mov r1,r1
+
+ adr r1,9b // boot ram base
+ ldr r5,8f // resume data offset ,from ram base
+ add r5,r5,r1 // resume data addr
+
+ ldr r3 ,[r5,#(RKPM_BOOTDATA_ARM_ERRATA_818325_F*4)]
+ ldr r4, = 0x200080b4 // armvoltage pwm resume
+ and r2, r3, #1
+ cmp r2, #0
+ beq pwm1
+ ldr r2, = 0x00100010 //pwm0
+ str r2, [r4]
+pwm1:
+ and r2, r3, #2
+ cmp r2, #0
+ beq pwm2
+ ldr r2, = 0x00400040 //pwm1
+ str r2, [r4]
+pwm2:
+ and r2, r3, #4
+ cmp r2, #0
+ beq sp_set
+ ldr r2, = 0x01000100//pwm2
+ str r2, [r4]
+
+sp_set: //sp
+ ldr sp,[r5,#(RKPM_BOOTDATA_CPUSP*4)] //sp
+
+ ldr r3,[r5,#(RKPM_BOOTDATA_DDR_F*4)]
+ //get SLP_DDR_NEED_RES ,if it is 1 ,ddr need to reusme
+ cmp r3,#1
+ bne res
+ ldr r1,[r5,#(RKPM_BOOTDATA_DDRCODE*4)] // ddr resume code
+ ldr r0,[r5,#(RKPM_BOOTDATA_DDRDATA*4)] //ddr resume data
+ blx r1
+res:
+ 1: mov r1,r1
+ // b 1b
+/*****************************************************************************/
+dram_resume:
+ ;//push {lr}
+ mov r2,#0x20000000 ;/*cru PA*/
+ mov r3,#0x20000000
+
+ str r3,[r2,#0x14];/*PLL no power-down*/
+
+ dsb sy
+ mov r2,r2
+ mov r2,r2
+
+dpll_lock:
+ ldr r3,[r2,#0x14]
+ tst r3,#400;/*DPLL lock*/
+
+ bne dpll_lock
+
+ ldr r3,=0x00100010;/*DPLL normal mode*/
+ str r3,[r2,#0x40]
+ dsb sy
+
+ mov r3,#0x40000
+ str r3,[r2,#0xd0];/*enable DDR PHY clock*/
+ mov r0,#1
+
+dealyus_uncache:
+ mov r1,#5
+ mul r0, r0, r1
+delay_loop:
+ subs r0, r0, #1
+ bne delay_loop
+
+ ldr r2,=0x2000a000
+ ldr r3,[r2,#0]
+ orr r3, r3, #0xc;/*phy soft de-reset*/
+ str r3,[r2,#0]
+ sub r2, r2, #0x2000; /*0x20008000*/
+ ldr r3,=0x40004
+ str r3,[r2,#0x148]
+
+ /*move to access status*/
+ sub r2, r2, #0x4000;/*0x20004000*/
+ mov r3, #4
+ str r3,[r2,#0x4];/*wake up */
+ dsb sy
+
+wait_access:
+ ldr r3,[r2,#0x8]
+ and r3, r3, #0x7
+ cmp r3, #3
+ bne wait_access
+
+
+ ldr r4, = 0x100a000c //printk
+ mov r1, #0x0e //msch ce xiao
+ str r1,[r4]
+
+ ldr r4, = 0x100a0010 //printk
+ mov r1, #0x0e //msch ce xiao
+
+ ldr pc, [r5,#(RKPM_BOOTDATA_CPUCODE*4)]
+8: .long (0x00+0x700)//RKPM_BOOT_CODE_OFFSET+RKPM_BOOT_CODE_SIZE
+ENDPROC(rk312x_pm_slp_cpu_resume)
+
projects / firefly-linux-kernel-4.4.55.git / commitdiff