[10:33:29:984]<4>[ 127.237239] [<
c07b5200>] (__mutex_lock_slowpath+0x1c0/0x22c) from [<
c07b529c>] (mutex_lock+0x30/0x48)
[10:33:30:000]<4>[ 127.237255] [<
c07b529c>] (mutex_lock+0x30/0x48) from [<
c057d32c>] (clk_prepare_lock+0x48/0xe0)
[10:33:30:015]<4>[ 127.237269] [<
c057d32c>] (clk_prepare_lock+0x48/0xe0) from [<
c057eea4>] (clk_prepare+0xc/0x24)
[10:33:30:031]<4>[ 127.237285] [<
c057eea4>] (clk_prepare+0xc/0x24) from [<
c0282df8>] (rk_pwm_config+0x20/0x74)
[10:33:30:031]<4>[ 127.237300] [<
c0282df8>] (rk_pwm_config+0x20/0x74) from [<
c0281904>] (pwm_config+0x54/0x60)
[10:33:30:031]<4>[ 127.237317] [<
c0281904>] (pwm_config+0x54/0x60) from [<
c02c0528>] (pwm_regulator_set_voltage+0xd0/0xf4)
struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
int ret;
- ret = clk_prepare_enable(pc->clk);
+ ret = clk_enable(pc->clk);
if (ret)
return ret;
ret = pc->config(chip, pwm, duty_ns, period_ns);
-
- clk_disable_unprepare(pc->clk);
+
+ clk_disable(pc->clk);
return 0;
}
struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
int ret = 0;
- ret = clk_prepare_enable(pc->clk);
+ ret = clk_enable(pc->clk);
if (ret)
return ret;
pc->set_enable(chip, pwm,false);
- clk_disable_unprepare(pc->clk);
+ clk_disable(pc->clk);
}
pc->chip.base = -1;
pc->chip.npwm = NUM_PWM;
spin_lock_init(&pc->lock);
+ clk_prepare(pc->clk);
/* Following enables PWM chip, channels would still be enabled individually through their control register */
DBG("npwm = %d, of_pwm_ncells =%d \n", pc->chip.npwm,pc->chip.of_pwm_n_cells);