clk: rockchip: rk3288: export isp and cif clk

Change-Id: I2d9e46383f94cbd8023ad042f3921364c191f852
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 07469dcd27ee68b460e3440dffc32d3356d02601..3503c8ebe82e4d62373d7b6a755d03b329ca3746 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -193,6 +193,7 @@ PNAME(mux_uart2_p)  = { "uart2_src", "uart2_frac", "xin24m" };
 PNAME(mux_uart3_p)     = { "uart3_src", "uart3_frac", "xin24m" };
 PNAME(mux_uart4_p)     = { "uart4_src", "uart4_frac", "xin24m" };
 PNAME(mux_vip_out_p)   = { "vip_src", "xin24m" };
+PNAME(mux_cifout_p)    = { "cif_src", "xin24m" };
 PNAME(mux_mac_p)       = { "mac_pll_src", "ext_gmac" };
 PNAME(mux_hsadcout_p)  = { "hsadc_src", "ext_hsadc" };
 PNAME(mux_edp_24m_p)   = { "ext_edp_24m", "xin24m" };
@@ -448,6 +449,12 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
                        RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
                        RK3288_CLKGATE_CON(3), 15, GFLAGS),
 
+       COMPOSITE_NOGATE(0, "cif_src", mux_pll_src_cpll_gpll_p, 0,
+                       RK3288_CLKSEL_CON(26), 8, 1, MFLAGS, 9, 5, DFLAGS),
+       COMPOSITE_NODIV(SCLK_CIFOUT, "sclk_cifout", mux_cifout_p, 0,
+                       RK3288_CLKSEL_CON(26), 15, 1, MFLAGS,
+                       RK3288_CLKGATE_CON(3), 7, GFLAGS),
+
        GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
                        RK3288_CLKGATE_CON(5), 12, GFLAGS),
        GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
@@ -801,7 +808,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 
        GATE(0, "pclk_vip_in", "ext_vip", 0, RK3288_CLKGATE_CON(16), 0, GFLAGS),
        INVERTER(0, "pclk_vip", "pclk_vip_in", RK3288_CLKSEL_CON(29), 4, IFLAGS),
-       GATE(0, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS),
+       GATE(PCLK_ISP_IN, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS),
        INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),
 };
 

diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
index 9a586e2d9c91fd3c81c74a3d927a2cd2973af563..e98b9e13189d53c9125508e45ce2f1e67e88cc6b 100644 (file)
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -88,6 +88,7 @@
 #define SCLK_PVTM_GPU          124
 #define SCLK_CRYPTO            125
 #define SCLK_MIPIDSI_24M       126
+#define SCLK_CIFOUT            127
 
 #define SCLK_MAC               151
 #define SCLK_MACREF_OUT                152
@@ -168,6 +169,7 @@
 #define PCLK_WDT               368
 #define PCLK_EFUSE256          369
 #define PCLK_EFUSE1024         370
+#define PCLK_ISP_IN            371
 
 /* hclk gates */
 #define HCLK_GPS               448