RK3368 DDR: fix HDMI display abnormal when ddr change freq

add parameter of lcdc type for mcu to fix HDMI display abnormal when do ddr
change freq. it must update bl30 to rk3368bl30_v2.09.bin at the same time.

Signed-off-by: Tang Yun ping <typ@rock-chips.com>

diff --git a/drivers/devfreq/ddr_rk3368.c b/drivers/devfreq/ddr_rk3368.c
index 7cd74af535c164a82d7acbf6921483565bef7560..87e2bcb725df4bc6d6d2c46ea3ce92916f9ea47d 100644 (file)
--- a/drivers/devfreq/ddr_rk3368.c
+++ b/drivers/devfreq/ddr_rk3368.c
@@ -77,9 +77,14 @@ static int _ddr_recalc_rate(void)
 static int _ddr_change_freq(u32 n_mhz)
 {
        u32 ret;
+       u32 lcdc_type;
+       struct rk_lcdc_driver *lcdc_dev = NULL;
 
        printk(KERN_DEBUG pr_fmt("In func %s,freq=%dMHz\n"), __func__, n_mhz);
-       if (scpi_ddr_set_clk_rate(n_mhz))
+       lcdc_dev = rk_get_lcdc_drv("lcdc0");
+       lcdc_type = lcdc_dev ? (u32)lcdc_dev->cur_screen->type : 0;
+       printk(KERN_DEBUG pr_fmt("lcdc type:%d\n"), lcdc_type);
+       if (scpi_ddr_set_clk_rate(n_mhz, lcdc_type))
                pr_info("set ddr freq timeout\n");
        ret = _ddr_recalc_rate() / 1000000;
        printk(KERN_DEBUG pr_fmt("Func %s out,freq=%dMHz\n"), __func__, ret);
@@ -253,7 +258,13 @@ static void ddr_init(u32 dram_speed_bin, u32 freq)
 {
        int lcdc_type;
 
-       lcdc_type = rockchip_get_screen_type();
+       struct rk_lcdc_driver *lcdc_dev = NULL;
+
+       lcdc_dev = rk_get_lcdc_drv("lcdc0");
+       if (lcdc_dev == NULL)
+               lcdc_type = 0;
+       else
+               lcdc_type = (u32)lcdc_dev->cur_screen->type;
        printk(KERN_DEBUG pr_fmt("In Func:%s,dram_speed_bin:%d,freq:%d,lcdc_type:%d\n"),
               __func__, dram_speed_bin, freq, lcdc_type);
        if (scpi_ddr_init(dram_speed_bin, freq, lcdc_type))

diff --git a/drivers/mailbox/scpi_protocol.c b/drivers/mailbox/scpi_protocol.c
index 10cefa0bb2fcc1a9a5bf285396f5ee9d0e71df02..51d8feb8b782cd871f9d6c9c9cd6e81ed4d9ec64 100644 (file)
--- a/drivers/mailbox/scpi_protocol.c
+++ b/drivers/mailbox/scpi_protocol.c
@@ -463,19 +463,20 @@ int scpi_ddr_init(u32 dram_speed_bin, u32 freq, u32 lcdc_type)
 }
 EXPORT_SYMBOL_GPL(scpi_ddr_init);
 
-int scpi_ddr_set_clk_rate(u32 rate)
+int scpi_ddr_set_clk_rate(u32 rate, u32 lcdc_type)
 {
        struct scpi_data_buf sdata;
        struct rockchip_mbox_msg mdata;
        struct __packed1 {
                u32 clk_rate;
+               u32 lcdc_type;
        } tx_buf;
        struct __packed2 {
                u32 status;
        } rx_buf;
 
        tx_buf.clk_rate = (u32)rate;
-
+       tx_buf.lcdc_type = (u32)lcdc_type;
        SCPI_SETUP_DBUF(sdata, mdata, SCPI_CL_DDR,
                        SCPI_DDR_SET_FREQ, tx_buf, rx_buf);
        return scpi_execute_cmd(&sdata);

diff --git a/include/linux/scpi_protocol.h b/include/linux/scpi_protocol.h
index dfa665ab034f58273e40794b77fe01fe7c0bd711..5219ff13fdb41ae2bcab1275b52825f3ec451b3b 100644 (file)
--- a/include/linux/scpi_protocol.h
+++ b/include/linux/scpi_protocol.h
@@ -41,7 +41,7 @@ int scpi_sys_set_mcu_state_suspend(void);
 int scpi_sys_set_mcu_state_resume(void);
 
 int scpi_ddr_init(u32 dram_speed_bin, u32 freq, u32 lcdc_type);
-int scpi_ddr_set_clk_rate(u32 rate);
+int scpi_ddr_set_clk_rate(u32 rate, u32 lcdc_type);
 int scpi_ddr_round_rate(u32 m_hz);
 int scpi_ddr_set_auto_self_refresh(u32 en);
 int scpi_ddr_bandwidth_get(struct ddr_bw_info *ddr_bw_ch0,