ARM64: dts: rk3399: assign clk parent and rate for SCLK_EMMC

Let's assign clk parent and rate for SCLK_EMMC to meet the
requiremen.

Change-Id: I3730a2124494da51717b1756f488f9df5bcd6423
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index e7d7dea724e323fe0a229a2fba48a2d4de97c153..8ec95c76c4befe39f522d4018f7560f855dbe01a 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -325,6 +325,9 @@
                interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
                clock-names = "clk_xin", "clk_ahb";
+               assigned-clocks = <&cru SCLK_EMMC>;
+               assigned-clock-parents = <&cru PLL_CPLL>;
+               assigned-clock-rates = <200000000>;
                phys = <&emmc_phy>;
                phy-names = "phy_arasan";
                status = "disabled";