drm: bridge: dw-hdmi: Reorder HDMI Initialization Step

There is a bug of pll lock detection in previous code.

/* Wait for PHY PLL lock */
msec = 5;
do {
	val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
	if (!val)
		break;
	...
} while (1)

while is break if pll is not lock yet, the real lock status may
be after the dw_hdmi_enable_video_path.

This bug is fixed in commit <a479fa5417b12fdf7aef8e41fdb99393e1c28581>
(FROMLIST: drm: bridge: dw-hdmi: Fix the PHY power up sequence)

But it introduced an new bug: hdmi output timing may be not stable,
the format shown on some TV is not a standard hdmi timing. For example,
1080P will be shown as 1922x1080 on LEADSTAR LD-1088.

After reorder the HDMI Initialization Step, phy initialization is
moved after the dw_hdmi_enable_video_path, this bug is fixed.

Change-Id: Id996978ceabcf1cce4bf83ddb84528c04fbb7583
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/dw-hdmi.c
index dc3fe9f0f1d2126bcd15214f765dd074c286175f..7feb580bce1f55978069e8c31e71a132c7c9deae 100644 (file)
--- a/drivers/gpu/drm/bridge/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/dw-hdmi.c
@@ -1904,15 +1904,15 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
        /* HDMI Initialization Step B.1 */
        hdmi_av_composer(hdmi, mode);
 
-       /* HDMI Initializateion Step B.2 */
+       /* HDMI Initialization Step B.2 */
+       dw_hdmi_enable_video_path(hdmi);
+
+       /* HDMI Initializateion Step B.3 */
        ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode);
        if (ret)
                return ret;
        hdmi->phy.enabled = true;
 
-       /* HDMI Initialization Step B.3 */
-       dw_hdmi_enable_video_path(hdmi);
-
        if (hdmi->sink_has_audio) {
                dev_dbg(hdmi->dev, "sink has audio support\n");