dmaengine: at_xdmac: fix spurious flag status for mem2mem transfers

commit 95da0c19d164f6df0b71a5187950f47d4b746e91 upstream.

When setting the channel configuration register, the perid field is not
set to 0 since it is useless for mem2mem transfers. Unfortunately, a
device has 0 as perid. It could cause spurious flags status because
the controller could mix some events from the two channels.
For that reason, use the highest perid value for mem2mem transfers since it
doesn't match the perid of other devices.

Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
index 9d05d7dbcfa94fc83f2634e4b5eddb6162f905a2..66c073fc8afc6e18809b9e429f783781a199f46c 100644 (file)
--- a/drivers/dma/at_xdmac.c
+++ b/drivers/dma/at_xdmac.c
@@ -864,8 +864,12 @@ at_xdmac_interleaved_queue_desc(struct dma_chan *chan,
         * access. Hopefully we can access DDR through both ports (at least on
         * SAMA5D4x), so we can use the same interface for source and dest,
         * that solves the fact we don't know the direction.
+        * ERRATA: Even if useless for memory transfers, the PERID has to not
+        * match the one of another channel. If not, it could lead to spurious
+        * flag status.
         */
-       u32                     chan_cc = AT_XDMAC_CC_DIF(0)
+       u32                     chan_cc = AT_XDMAC_CC_PERID(0x3f)
+                                       | AT_XDMAC_CC_DIF(0)
                                        | AT_XDMAC_CC_SIF(0)
                                        | AT_XDMAC_CC_MBSIZE_SIXTEEN
                                        | AT_XDMAC_CC_TYPE_MEM_TRAN;
@@ -1042,8 +1046,12 @@ at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
         * access DDR through both ports (at least on SAMA5D4x), so we can use
         * the same interface for source and dest, that solves the fact we
         * don't know the direction.
+        * ERRATA: Even if useless for memory transfers, the PERID has to not
+        * match the one of another channel. If not, it could lead to spurious
+        * flag status.
         */
-       u32                     chan_cc = AT_XDMAC_CC_DAM_INCREMENTED_AM
+       u32                     chan_cc = AT_XDMAC_CC_PERID(0x3f)
+                                       | AT_XDMAC_CC_DAM_INCREMENTED_AM
                                        | AT_XDMAC_CC_SAM_INCREMENTED_AM
                                        | AT_XDMAC_CC_DIF(0)
                                        | AT_XDMAC_CC_SIF(0)
@@ -1144,8 +1152,12 @@ static struct at_xdmac_desc *at_xdmac_memset_create_desc(struct dma_chan *chan,
         * access. Hopefully we can access DDR through both ports (at least on
         * SAMA5D4x), so we can use the same interface for source and dest,
         * that solves the fact we don't know the direction.
+        * ERRATA: Even if useless for memory transfers, the PERID has to not
+        * match the one of another channel. If not, it could lead to spurious
+        * flag status.
         */
-       u32                     chan_cc = AT_XDMAC_CC_DAM_UBS_AM
+       u32                     chan_cc = AT_XDMAC_CC_PERID(0x3f)
+                                       | AT_XDMAC_CC_DAM_UBS_AM
                                        | AT_XDMAC_CC_SAM_INCREMENTED_AM
                                        | AT_XDMAC_CC_DIF(0)
                                        | AT_XDMAC_CC_SIF(0)