ARM: errata: Workaround for Cortex-A12 erratum 821420

On Cortex-A12 (r0p0, r0p1), in very rare timing conditions, a sequence of
VMOV to Core registers instructions, for which the second one is in the
shadow of a branch or abort, can lead to a deadlock when the VMOV
instructions are issued out-of-order. This workaround setting bit 1 of
the Internal Feature Register prevents the erratum.

Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f5c385a93edebb06bc0d5c89c61a95f2cdb86b52..8f754f2a783bc4a0fefa6267e049c3f5541fd898 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1373,6 +1373,16 @@ config ARM_ERRATA_818325
          prevents the erratum. This bit disables an optimisation applied to a
          sequence of 2 instructions that use opposing condition codes.
 
+config ARM_ERRATA_821420
+       bool "ARM errata: A sequence of VMOV to core registers instruction might lead to a deadlock"
+       depends on CPU_V7
+       help
+         This option enables the workaround for the 821420 Cortex-A12 (r0p0,
+         r0p1) erratum. In very rare timing conditions, a sequence of VMOV to
+         Core registers instructions, for which the second one is in the
+         shadow of a branch or abort, can lead to a deadlock when the VMOV
+         instructions are issued out-of-order.
+
 endmenu
 
 source "arch/arm/common/Kconfig"

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 34862572f2170ffa87d8da7218fe1b2ff511b6c9..2de7342c85e102ac6d124c1d734ff084ca614fb4 100644 (file)
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -340,6 +340,14 @@ __v7_setup:
        mcreq   p15, 0, r10, c15, c0, 1         @ write diagnostic register
        isb
 #endif
+#ifdef CONFIG_ARM_ERRATA_821420
+       teq     r6, #0x00                       @ present in r0p0
+       teqne   r6, #0x01                       @ present in r0p1
+       mrceq   p15, 0, r10, c15, c0, 2
+       orreq   r10, r10, #1 << 1
+       mcreq   p15, 0, r10, c15, c0, 2
+       isb
+#endif
 
 4:     mov     r10, #0
        mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate