clk: rockchip: rk3368: add ddrc clock support

Add a ddrc clock into clk branches, so we can do ddr frequency
scaling on rk3368 platform in future.

Change-Id: Ie7fd2e8d8bdf8b9ff843ca13e848f772adaa109a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index e4554a3ca525d82d22b8dac079d4ba9515d870d6..a5e5050e4ccf07283477381f850cac826afed59c 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -338,6 +338,9 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
                        RK3368_CLKGATE_CON(1), 8, GFLAGS),
        GATE(0, "gpll_ddr", "gpll", 0,
                        RK3368_CLKGATE_CON(1), 9, GFLAGS),
                        RK3368_CLKGATE_CON(1), 8, GFLAGS),
        GATE(0, "gpll_ddr", "gpll", 0,
                        RK3368_CLKGATE_CON(1), 9, GFLAGS),

+       COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
+                       RK3368_CLKSEL_CON(13), 4, 1, 0, 0, ROCKCHIP_DDRCLK_SCPI),
+

        COMPOSITE_NOGATE_DIVTBL(0, "ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
                        RK3368_CLKSEL_CON(13), 4, 1, MFLAGS, 0, 2, DFLAGS, div_ddrphy_t),
 
        COMPOSITE_NOGATE_DIVTBL(0, "ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
                        RK3368_CLKSEL_CON(13), 4, 1, MFLAGS, 0, 2, DFLAGS, div_ddrphy_t),