serial: 8250_mid: recognize interrupt source in handler

commit c42850f1ae7e70056f852e67bb9dddf927853b47 upstream.

There is a special register that shows interrupt status by source. In
particular case the source can be a combination of DMA Tx, DMA Rx, and UART.

Read the register and call the handlers only for sources that request an
interrupt.

Fixes: 6ede6dcd87aa ("serial: 8250_mid: add support for DMA engine handling from UART MMIO")
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/tty/serial/8250/8250_mid.c b/drivers/tty/serial/8250/8250_mid.c
index 7aa6ef81ca93eaac8d0231c9e93535f17a0d1b0a..ed489880e62b3ec4bd988dc833885afc68d7d367 100644 (file)
--- a/drivers/tty/serial/8250/8250_mid.c
+++ b/drivers/tty/serial/8250/8250_mid.c
@@ -25,6 +25,7 @@
 #define PCI_DEVICE_ID_INTEL_DNV_UART   0x19d8
 
 /* Intel MID Specific registers */
+#define INTEL_MID_UART_DNV_FISR                0x08
 #define INTEL_MID_UART_PS              0x30
 #define INTEL_MID_UART_MUL             0x34
 #define INTEL_MID_UART_DIV             0x38
@@ -90,16 +91,16 @@ static int tng_setup(struct mid8250 *mid, struct uart_port *p)
 static int dnv_handle_irq(struct uart_port *p)
 {
        struct mid8250 *mid = p->private_data;
-       int ret;
-
-       ret = hsu_dma_irq(&mid->dma_chip, 0);
-       ret |= hsu_dma_irq(&mid->dma_chip, 1);
-
-       /* For now, letting the HW generate separate interrupt for the UART */
-       if (ret)
-               return ret;
-
-       return serial8250_handle_irq(p, serial_port_in(p, UART_IIR));
+       unsigned int fisr = serial_port_in(p, INTEL_MID_UART_DNV_FISR);
+       int ret = IRQ_NONE;
+
+       if (fisr & BIT(2))
+               ret |= hsu_dma_irq(&mid->dma_chip, 1);
+       if (fisr & BIT(1))
+               ret |= hsu_dma_irq(&mid->dma_chip, 0);
+       if (fisr & BIT(0))
+               ret |= serial8250_handle_irq(p, serial_port_in(p, UART_IIR));
+       return ret;
 }
 
 #define DNV_DMA_CHAN_OFFSET 0x80