arm64: barriers: make use of barrier options with explicit barriers

When calling our low-level barrier macros directly, we can often suffice
with more relaxed behaviour than the default "all accesses, full system"
option.

This patch updates the users of dsb() to specify the option which they
actually require.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
(cherry picked from commit 98f7685ee69f871ba991089cb9685f0da07517ea)
Signed-off-by: Mark Brown <broonie@linaro.org>
Conflicts:
	arch/arm64/kvm/sys_regs.c

diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h
index 2306cd19505591bfb13a22d369e8da45c5f6ffb5..c98d0a88916a4bfd824f11a4014e9d719518a24b 100644 (file)
--- a/arch/arm64/include/asm/barrier.h
+++ b/arch/arm64/include/asm/barrier.h
@@ -28,7 +28,7 @@
 #define dmb(opt)       asm volatile("dmb sy" : : : "memory")
 #define dsb(opt)       asm volatile("dsb sy" : : : "memory")
 
-#define mb()           dsb()
+#define mb()           dsb(sy)
 #define rmb()          asm volatile("dsb ld" : : : "memory")
 #define wmb()          asm volatile("dsb st" : : : "memory")
 

diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h
index 889324981aa4f569a77e6a5385897b6493c85526..24bc1d2ebdb9885ec0e56f8dba3f2b3e88b3385b 100644 (file)
--- a/arch/arm64/include/asm/cacheflush.h
+++ b/arch/arm64/include/asm/cacheflush.h
@@ -116,7 +116,7 @@ extern void flush_dcache_page(struct page *);
 static inline void __flush_icache_all(void)
 {
        asm("ic ialluis");
-       dsb();
+       dsb(ish);
 }
 
 #define flush_dcache_mmap_lock(mapping) \
@@ -143,7 +143,7 @@ static inline void flush_cache_vmap(unsigned long start, unsigned long end)
         * set_pte_at() called from vmap_pte_range() does not
         * have a DSB after cleaning the cache line.
         */
-       dsb();
+       dsb(ish);
 }
 
 static inline void flush_cache_vunmap(unsigned long start, unsigned long end)

diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 0359c2335b9c899c06324d9fc7d0fe845cde6485..8af30ab8d3c221a1f3c64e5323533657c2fb5449 100644 (file)
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -299,7 +299,7 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
 {
        *pmdp = pmd;
-       dsb();
+       dsb(ishst);
 }
 
 static inline void pmd_clear(pmd_t *pmdp)
@@ -329,7 +329,7 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd)
 static inline void set_pud(pud_t *pudp, pud_t pud)
 {
        *pudp = pud;
-       dsb();
+       dsb(ishst);
 }
 
 static inline void pud_clear(pud_t *pudp)

diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index 8b482035cfc2434bdba34d3e24e6308ac01f423e..3083a08f96225c152822d5fb169b3336cc7f9648 100644 (file)
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -72,9 +72,9 @@ extern struct cpu_tlb_fns cpu_tlb;
  */
 static inline void flush_tlb_all(void)
 {
-       dsb();
+       dsb(ishst);
        asm("tlbi       vmalle1is");
-       dsb();
+       dsb(ish);
        isb();
 }
 
@@ -82,9 +82,9 @@ static inline void flush_tlb_mm(struct mm_struct *mm)
 {
        unsigned long asid = (unsigned long)ASID(mm) << 48;
 
-       dsb();
+       dsb(ishst);
        asm("tlbi       aside1is, %0" : : "r" (asid));
-       dsb();
+       dsb(ish);
 }
 
 static inline void flush_tlb_page(struct vm_area_struct *vma,
@@ -93,9 +93,9 @@ static inline void flush_tlb_page(struct vm_area_struct *vma,
        unsigned long addr = uaddr >> 12 |
                ((unsigned long)ASID(vma->vm_mm) << 48);
 
-       dsb();
+       dsb(ishst);
        asm("tlbi       vae1is, %0" : : "r" (addr));
-       dsb();
+       dsb(ish);
 }
 
 /*
@@ -114,7 +114,7 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
         * set_pte() does not have a DSB, so make sure that the page table
         * write is visible.
         */
-       dsb();
+       dsb(ishst);
 }
 
 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)

diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 75af46648f2671e90348c9d40eb438bf09b45afd..57bd961f29176002dd911e8991d462da924e1ec6 100644 (file)
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -306,7 +306,7 @@ struct task_struct *__switch_to(struct task_struct *prev,
         * Complete any pending TLB or cache maintenance on this CPU in case
         * the thread migrates to a different CPU.
         */
-       dsb();
+       dsb(ish);
 
        /* the actual thread switch */
        last = cpu_switch_to(prev, next);