arm64: dts: rockchip: add ehci/ochi and u2phy nodes for rk3368
authorFrank Wang <frank.wang@rock-chips.com>
Wed, 15 Mar 2017 07:10:26 +0000 (15:10 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Thu, 16 Mar 2017 00:34:03 +0000 (08:34 +0800)
This adds configure ehci/ohci and u2phy nodes for rk3368 SoC.

Change-Id: I80cc311d7c14abc56084118baccf87501d44263e
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
arch/arm64/boot/dts/rockchip/rk3368.dtsi

index c5eeb17..c72a348 100644 (file)
 
        usb_host0_ehci: usb@ff500000 {
                compatible = "generic-ehci";
-               reg = <0x0 0xff500000 0x0 0x100>;
+               reg = <0x0 0xff500000 0x0 0x20000>;
                interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&cru HCLK_HOST0>;
-               clock-names = "usbhost";
+               clocks = <&cru HCLK_HOST0>, <&u2phy>;
+               clock-names = "usbhost", "utmi";
+               phys = <&u2phy_host>;
+               phy-names = "usb";
+               status = "disabled";
+       };
+
+       usb_host0_ohci: usb@ff520000 {
+               compatible = "generic-ohci";
+               reg = <0x0 0xff520000 0x0 0x20000>;
+               interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru HCLK_HOST0>, <&u2phy>;
+               clock-names = "usbhost", "utmi";
+               phys = <&u2phy_host>;
+               phy-names = "usb";
                status = "disabled";
        };
 
        grf: syscon@ff770000 {
                compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
                reg = <0x0 0xff770000 0x0 0x1000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
 
                io_domains: io-domains {
                        compatible = "rockchip,rk3368-io-voltage-domain";
                        status = "disabled";
                };
+
+               u2phy: usb2-phy@700 {
+                       compatible = "rockchip,rk3368-usb2phy";
+                       reg = <0x700 0x2c>;
+                       clocks = <&cru SCLK_OTGPHY0>;
+                       clock-names = "phyclk";
+                       #clock-cells = <0>;
+                       clock-output-names = "usbotg_out";
+                       assigned-clocks = <&cru SCLK_USBPHY480M>;
+                       assigned-clock-parents = <&u2phy>;
+                       status = "disabled";
+
+                       u2phy_host: host-port {
+                               #phy-cells = <0>;
+                               interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-names = "linestate";
+                               status = "disabled";
+                       };
+               };
        };
 
        wdt: watchdog@ff800000 {