UPSTREAM: usb: dwc2: Rename dwc2_core_reset()
authorJohn Youn <John.Youn@synopsys.com>
Thu, 17 Dec 2015 19:15:49 +0000 (11:15 -0800)
committerHuang, Tao <huangtao@rock-chips.com>
Tue, 3 Jan 2017 10:47:44 +0000 (18:47 +0800)
Renamed dwc2_core_reset() to dwc2_core_reset_and_force_dr_mode(). This
describes what it is doing more accurately. This is in preparation of
introducing a plain dwc2_core_reset() function that only performs the
reset and doesn't force the mode.

Change-Id: I1c0c17ed45cfcffe30561eaccd773d489e3c980c
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 6d58f346a61ff50eda740e6216e9829e572d75c8)

drivers/usb/dwc2/core.c
drivers/usb/dwc2/core.h
drivers/usb/dwc2/platform.c

index 62505068abf2e2a90daf38807ca3e0d73c5e6cfa..eb291c9e3c169e2d55c71e025b8ff940aabffb01 100644 (file)
@@ -481,7 +481,7 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
  * Do core a soft reset of the core.  Be careful with this because it
  * resets all the internal state machines of the core.
  */
-int dwc2_core_reset(struct dwc2_hsotg *hsotg)
+int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg)
 {
        u32 greset;
        int count = 0;
@@ -561,7 +561,7 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
                        dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 
                        /* Reset after a PHY select */
-                       retval = dwc2_core_reset(hsotg);
+                       retval = dwc2_core_reset_and_force_dr_mode(hsotg);
 
                        if (retval) {
                                dev_err(hsotg->dev,
@@ -640,7 +640,7 @@ static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
                dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 
                /* Reset after setting the PHY parameters */
-               retval = dwc2_core_reset(hsotg);
+               retval = dwc2_core_reset_and_force_dr_mode(hsotg);
                if (retval) {
                        dev_err(hsotg->dev,
                                "%s: Reset failed, aborting", __func__);
@@ -805,7 +805,7 @@ int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
         * needed to in order to properly detect various parameters).
         */
        if (!initial_setup) {
-               retval = dwc2_core_reset(hsotg);
+               retval = dwc2_core_reset_and_force_dr_mode(hsotg);
                if (retval) {
                        dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
                                        __func__);
index 3cfdfb823979907946187d9ce0813d36f5588a55..be2985429177c8ed4f989b4cc4075b9245c90dfb 100644 (file)
@@ -908,7 +908,7 @@ enum dwc2_halt_status {
  * The following functions support initialization of the core driver component
  * and the DWC_otg controller
  */
-extern int dwc2_core_reset(struct dwc2_hsotg *hsotg);
+extern int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg);
 extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg);
 extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg);
 extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore);
index 06d2b7a2706a217a7d81c34169dd1eb562901e78..91203aca7256762b0128d2cab35a941ee6da92d9 100644 (file)
@@ -469,7 +469,7 @@ static int dwc2_driver_probe(struct platform_device *dev)
         * Reset before dwc2_get_hwparams() then it could get power-on real
         * reset value form registers.
         */
-       dwc2_core_reset(hsotg);
+       dwc2_core_reset_and_force_dr_mode(hsotg);
 
        /* Detect config values from hardware */
        retval = dwc2_get_hwparams(hsotg);