UPSTREAM: usb: dwc2: Reorder AHBIDLE and CSFTRST in dwc2_core_reset()

According to the databook, the core soft reset should be done before
checking for AHBIDLE. The gadget version of core reset had it correct
but the hcd version did not. This fixes the hcd version.

Change-Id: I49540085036982e6c496a3b911805f0b67fa79e1
Signed-off-by: John Youn <johnyoun@synopsys.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(cherry picked from commit b8ccc593eeeacde0e6794c4dcec0a57eba7356e6)

diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
index 60822bc967ddc8d3097f0a884a30ff5ea5e3241e..710f98e4daec7f5ef609d0f67d4cb391ac80e8d9 100644 (file)
--- a/drivers/usb/dwc2/core.c
+++ b/drivers/usb/dwc2/core.c
@@ -489,32 +489,33 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg)
 
        dev_vdbg(hsotg->dev, "%s()\n", __func__);
 
-       /* Wait for AHB master IDLE state */
+       /* Core Soft Reset */
+       greset = dwc2_readl(hsotg->regs + GRSTCTL);
+       greset |= GRSTCTL_CSFTRST;
+       dwc2_writel(greset, hsotg->regs + GRSTCTL);
        do {
                udelay(1);
                greset = dwc2_readl(hsotg->regs + GRSTCTL);
                if (++count > 50) {
                        dev_warn(hsotg->dev,
-                                "%s() HANG! AHB Idle GRSTCTL=%0x\n",
+                                "%s() HANG! Soft Reset GRSTCTL=%0x\n",
                                 __func__, greset);
                        return -EBUSY;
                }
-       } while (!(greset & GRSTCTL_AHBIDLE));
+       } while (greset & GRSTCTL_CSFTRST);
 
-       /* Core Soft Reset */
+       /* Wait for AHB master IDLE state */
        count = 0;
-       greset |= GRSTCTL_CSFTRST;
-       dwc2_writel(greset, hsotg->regs + GRSTCTL);
        do {
                udelay(1);
                greset = dwc2_readl(hsotg->regs + GRSTCTL);
                if (++count > 50) {
                        dev_warn(hsotg->dev,
-                                "%s() HANG! Soft Reset GRSTCTL=%0x\n",
+                                "%s() HANG! AHB Idle GRSTCTL=%0x\n",
                                 __func__, greset);
                        return -EBUSY;
                }
-       } while (greset & GRSTCTL_CSFTRST);
+       } while (!(greset & GRSTCTL_AHBIDLE));
 
        if (hsotg->dr_mode == USB_DR_MODE_HOST) {
                gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);