rk: move cpu_axi.h from arch/arm/mach-rockchip to include/linux/rockchip

Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

diff --git a/arch/arm/mach-rockchip/common.c b/arch/arm/mach-rockchip/common.c
index eded0645795d5bfc9aa62d28ccb99bfd06a0896e..684180eb998889fac654ec8d34d51d884a2b94bc 100755 (executable)
--- a/arch/arm/mach-rockchip/common.c
+++ b/arch/arm/mach-rockchip/common.c
@@ -25,9 +25,9 @@
 #include <asm/hardware/cache-l2x0.h>
 #endif
 #include <linux/rockchip/common.h>
+#include <linux/rockchip/cpu_axi.h>
 #include <linux/rockchip/pmu.h>
 #include <linux/memblock.h>
-#include "cpu_axi.h"
 #include "loader.h"
 #include "sram.h"
 

diff --git a/arch/arm/mach-rockchip/cpu_axi.h b/arch/arm/mach-rockchip/cpu_axi.h
deleted file mode 100644 (file)
index 9af5a7a..0000000
--- a/arch/arm/mach-rockchip/cpu_axi.h
+++ /dev/null
@@ -1,128 +0,0 @@
-#ifndef __CPU_AXI_H
-#define __CPU_AXI_H
-
-#define CPU_AXI_QOS_PRIORITY    0x08
-#define CPU_AXI_QOS_MODE        0x0c
-#define CPU_AXI_QOS_BANDWIDTH   0x10
-#define CPU_AXI_QOS_SATURATION  0x14
-#define CPU_AXI_QOS_EXTCONTROL  0x18
-
-#define CPU_AXI_QOS_MODE_NONE           0
-#define CPU_AXI_QOS_MODE_FIXED          1
-#define CPU_AXI_QOS_MODE_LIMITER        2
-#define CPU_AXI_QOS_MODE_REGULATOR      3
-
-#define CPU_AXI_QOS_PRIORITY_LEVEL(h, l) \
-       ((((h) & 3) << 8) | (((h) & 3) << 2) | ((l) & 3))
-#define CPU_AXI_SET_QOS_PRIORITY(h, l, base) \
-       writel_relaxed(CPU_AXI_QOS_PRIORITY_LEVEL(h, l), base + CPU_AXI_QOS_PRIORITY)
-
-#define CPU_AXI_SET_QOS_MODE(mode, base) \
-       writel_relaxed((mode) & 3, base + CPU_AXI_QOS_MODE)
-
-#define CPU_AXI_SET_QOS_BANDWIDTH(bandwidth, base) \
-       writel_relaxed((bandwidth) & 0x7ff, base + CPU_AXI_QOS_BANDWIDTH)
-
-#define CPU_AXI_SET_QOS_SATURATION(saturation, base) \
-       writel_relaxed((saturation) & 0x3ff, base + CPU_AXI_QOS_SATURATION)
-
-#define CPU_AXI_SET_QOS_EXTCONTROL(extcontrol, base) \
-       writel_relaxed((extcontrol) & 7, base + CPU_AXI_QOS_EXTCONTROL)
-
-#define CPU_AXI_QOS_NUM_REGS 5
-#define CPU_AXI_SAVE_QOS(array, base) do { \
-       array[0] = readl_relaxed(base + CPU_AXI_QOS_PRIORITY); \
-       array[1] = readl_relaxed(base + CPU_AXI_QOS_MODE); \
-       array[2] = readl_relaxed(base + CPU_AXI_QOS_BANDWIDTH); \
-       array[3] = readl_relaxed(base + CPU_AXI_QOS_SATURATION); \
-       array[4] = readl_relaxed(base + CPU_AXI_QOS_EXTCONTROL); \
-} while (0)
-#define CPU_AXI_RESTORE_QOS(array, base) do { \
-       writel_relaxed(array[0], base + CPU_AXI_QOS_PRIORITY); \
-       writel_relaxed(array[1], base + CPU_AXI_QOS_MODE); \
-       writel_relaxed(array[2], base + CPU_AXI_QOS_BANDWIDTH); \
-       writel_relaxed(array[3], base + CPU_AXI_QOS_SATURATION); \
-       writel_relaxed(array[4], base + CPU_AXI_QOS_EXTCONTROL); \
-} while (0)
-
-#define RK3188_CPU_AXI_DMAC_QOS_VIRT    (RK_CPU_AXI_BUS_VIRT + 0x1000)
-#define RK3188_CPU_AXI_CPU0_QOS_VIRT    (RK_CPU_AXI_BUS_VIRT + 0x2000)
-#define RK3188_CPU_AXI_CPU1R_QOS_VIRT   (RK_CPU_AXI_BUS_VIRT + 0x2080)
-#define RK3188_CPU_AXI_CPU1W_QOS_VIRT   (RK_CPU_AXI_BUS_VIRT + 0x2100)
-#define RK3188_CPU_AXI_PERI_QOS_VIRT    (RK_CPU_AXI_BUS_VIRT + 0x4000)
-#define RK3188_CPU_AXI_GPU_QOS_VIRT     (RK_CPU_AXI_BUS_VIRT + 0x5000)
-#define RK3188_CPU_AXI_VPU_QOS_VIRT     (RK_CPU_AXI_BUS_VIRT + 0x6000)
-#define RK3188_CPU_AXI_LCDC0_QOS_VIRT   (RK_CPU_AXI_BUS_VIRT + 0x7000)
-#define RK3188_CPU_AXI_CIF0_QOS_VIRT    (RK_CPU_AXI_BUS_VIRT + 0x7080)
-#define RK3188_CPU_AXI_IPP_QOS_VIRT     (RK_CPU_AXI_BUS_VIRT + 0x7100)
-#define RK3188_CPU_AXI_LCDC1_QOS_VIRT   (RK_CPU_AXI_BUS_VIRT + 0x7180)
-#define RK3188_CPU_AXI_CIF1_QOS_VIRT    (RK_CPU_AXI_BUS_VIRT + 0x7200)
-#define RK3188_CPU_AXI_RGA_QOS_VIRT     (RK_CPU_AXI_BUS_VIRT + 0x7280)
-
-/* service core */
-#define RK3288_SERVICE_CORE_VIRT                RK_CPU_AXI_BUS_VIRT
-#define RK3288_CPU_AXI_CPUM_R_QOS_VIRT          (RK3288_SERVICE_CORE_VIRT + 0x80)
-#define RK3288_CPU_AXI_CPUM_W_QOS_VIRT          (RK3288_SERVICE_CORE_VIRT + 0x100)
-#define RK3288_CPU_AXI_CPUP_QOS_VIRT            (RK3288_SERVICE_CORE_VIRT + 0x0)
-/* service dmac */
-#define RK3288_SERVICE_DMAC_VIRT                (RK3288_SERVICE_CORE_VIRT + RK3288_SERVICE_CORE_SIZE)
-#define RK3288_CPU_AXI_BUS_DMAC_QOS_VIRT        (RK3288_SERVICE_DMAC_VIRT + 0x0)
-#define RK3288_CPU_AXI_CCP_QOS_VIRT             (RK3288_SERVICE_DMAC_VIRT + 0x180)
-#define RK3288_CPU_AXI_CRYPTO_QOS_VIRT          (RK3288_SERVICE_DMAC_VIRT + 0x100)
-#define RK3288_CPU_AXI_CCS_QOS_VIRT             (RK3288_SERVICE_DMAC_VIRT + 0x200)
-#define RK3288_CPU_AXI_HOST_QOS_VIRT            (RK3288_SERVICE_DMAC_VIRT + 0x80)
-/* service gpu */
-#define RK3288_SERVICE_GPU_VIRT                 (RK3288_SERVICE_DMAC_VIRT + RK3288_SERVICE_DMAC_SIZE)
-#define RK3288_CPU_AXI_GPU_R_QOS_VIRT           (RK3288_SERVICE_GPU_VIRT + 0x0)
-#define RK3288_CPU_AXI_GPU_W_QOS_VIRT           (RK3288_SERVICE_GPU_VIRT + 0x80)
-/* service peri */
-#define RK3288_SERVICE_PERI_VIRT                (RK3288_SERVICE_GPU_VIRT + RK3288_SERVICE_GPU_SIZE)
-#define RK3288_CPU_AXI_PERI_QOS_VIRT            (RK3288_SERVICE_PERI_VIRT + 0x0)
-/* service bus */
-#define RK3288_SERVICE_BUS_VIRT                 (RK3288_SERVICE_PERI_VIRT + RK3288_SERVICE_PERI_SIZE)
-/* service vio */
-#define RK3288_SERVICE_VIO_VIRT                 (RK3288_SERVICE_BUS_VIRT + RK3288_SERVICE_BUS_SIZE)
-#define RK3288_CPU_AXI_VIO0_IEP_QOS_VIRT        (RK3288_SERVICE_VIO_VIRT + 0x500)
-#define RK3288_CPU_AXI_VIO0_VIP_QOS_VIRT        (RK3288_SERVICE_VIO_VIRT + 0x480)
-#define RK3288_CPU_AXI_VIO0_VOP_QOS_VIRT        (RK3288_SERVICE_VIO_VIRT + 0x400)
-#define RK3288_CPU_AXI_VIO1_ISP_R_QOS_VIRT      (RK3288_SERVICE_VIO_VIRT + 0x900)
-#define RK3288_CPU_AXI_VIO1_ISP_W0_QOS_VIRT     (RK3288_SERVICE_VIO_VIRT + 0x100)
-#define RK3288_CPU_AXI_VIO1_ISP_W1_QOS_VIRT     (RK3288_SERVICE_VIO_VIRT + 0x180)
-#define RK3288_CPU_AXI_VIO1_VOP_QOS_VIRT        (RK3288_SERVICE_VIO_VIRT + 0x0)
-#define RK3288_CPU_AXI_VIO2_RGA_R_QOS_VIRT      (RK3288_SERVICE_VIO_VIRT + 0x800)
-#define RK3288_CPU_AXI_VIO2_RGA_W_QOS_VIRT      (RK3288_SERVICE_VIO_VIRT + 0x880)
-/* service video */
-#define RK3288_SERVICE_VIDEO_VIRT               (RK3288_SERVICE_VIO_VIRT + RK3288_SERVICE_VIO_SIZE)
-#define RK3288_CPU_AXI_VIDEO_QOS_VIRT           (RK3288_SERVICE_VIDEO_VIRT + 0x0)
-/* service hevc */
-#define RK3288_SERVICE_HEVC_VIRT                (RK3288_SERVICE_VIDEO_VIRT + RK3288_SERVICE_VIDEO_SIZE)
-#define RK3288_CPU_AXI_HEVC_R_QOS_VIRT          (RK3288_SERVICE_HEVC_VIRT + 0x0)
-#define RK3288_CPU_AXI_HEVC_W_QOS_VIRT          (RK3288_SERVICE_HEVC_VIRT + 0x100)
-
-#define RK312X_CPU_AXI_QOS_NUM_REGS 4
-#define RK312X_CPU_AXI_SAVE_QOS(array, base) do { \
-       array[0] = readl_relaxed(base + CPU_AXI_QOS_PRIORITY); \
-       array[1] = readl_relaxed(base + CPU_AXI_QOS_MODE); \
-       array[2] = readl_relaxed(base + CPU_AXI_QOS_BANDWIDTH); \
-       array[3] = readl_relaxed(base + CPU_AXI_QOS_SATURATION); \
-} while (0)
-#define RK312X_CPU_AXI_RESTORE_QOS(array, base) do { \
-       writel_relaxed(array[0], base + CPU_AXI_QOS_PRIORITY); \
-       writel_relaxed(array[1], base + CPU_AXI_QOS_MODE); \
-       writel_relaxed(array[2], base + CPU_AXI_QOS_BANDWIDTH); \
-       writel_relaxed(array[3], base + CPU_AXI_QOS_SATURATION); \
-} while (0)
-#define RK312X_SERVICE_VIO_VIRT                 (RK_CPU_AXI_BUS_VIRT + 0x7000)
-
-#define RK312X_CPU_AXI_VIO_RGA_QOS_VIRT        (RK312X_SERVICE_VIO_VIRT)
-#define RK312X_CPU_AXI_VIO_EBC_QOS_VIRT        (RK312X_SERVICE_VIO_VIRT + 0x80)
-#define RK312X_CPU_AXI_VIO_IEP_QOS_VIRT      (RK312X_SERVICE_VIO_VIRT + 0x100)
-#define RK312X_CPU_AXI_VIO_LCDC0_QOS_VIRT     (RK312X_SERVICE_VIO_VIRT + 0x180)
-#define RK312X_CPU_AXI_VIO_VIP0_QOS_VIRT     (RK312X_SERVICE_VIO_VIRT + 0x200)
-
-#define RK312X_SERVICE_GPU_VIRT                 (RK_CPU_AXI_BUS_VIRT + 0x5000)
-#define RK312X_CPU_AXI_GPU_QOS_VIRT        (RK312X_SERVICE_GPU_VIRT)
-
-#define RK312X_SERVICE_VIDEO_VIRT                 (RK_CPU_AXI_BUS_VIRT + 0x6000)
-#define RK312X_CPU_AXI_VIDEO_QOS_VIRT        (RK312X_SERVICE_VIDEO_VIRT)
-#endif

diff --git a/arch/arm/mach-rockchip/ddr_freq.c b/arch/arm/mach-rockchip/ddr_freq.c
index 7bda5775a8dd61a0c635f264b06f176004a1d0ca..b5b31e02cd79a7916b836a7ef9a70ae2cba036df 100644 (file)
--- a/arch/arm/mach-rockchip/ddr_freq.c
+++ b/arch/arm/mach-rockchip/ddr_freq.c
@@ -21,6 +21,7 @@
 #include <asm/tlbflush.h>
 #include <linux/vmalloc.h>
 #include <linux/rockchip/common.h>
+#include <linux/rockchip/cpu_axi.h>
 #include <linux/rockchip/dvfs.h>
 #include <dt-bindings/clock/ddr.h>
 #include <dt-bindings/clock/rk_system_status.h>
@@ -30,7 +31,6 @@
 #include <linux/clk-private.h>
 #include <linux/rockchip/cpu.h>
 #include "../../../drivers/clk/rockchip/clk-pd.h"
-#include "cpu_axi.h"
 
 static DECLARE_COMPLETION(ddrfreq_completion);
 static DEFINE_MUTEX(ddrfreq_mutex);

diff --git a/arch/arm/mach-rockchip/ddr_rk3036.c b/arch/arm/mach-rockchip/ddr_rk3036.c
index 518cac4d935365bee049a63dc1d4a2357ec2324a..3b0ee4ab1ff49591c92fe40c4b0dd37f51fda096 100755 (executable)
--- a/arch/arm/mach-rockchip/ddr_rk3036.c
+++ b/arch/arm/mach-rockchip/ddr_rk3036.c
@@ -21,9 +21,9 @@
 #include <asm/tlbflush.h>
 #include <linux/cpu.h>
 #include <dt-bindings/clock/ddr.h>
+#include <linux/rockchip/cpu_axi.h>
 #include <linux/rockchip/cru.h>
 #include <linux/rk_fb.h>
-#include "cpu_axi.h"
 
 
 typedef uint32_t uint32 ;

diff --git a/arch/arm/mach-rockchip/ddr_rk3126.c b/arch/arm/mach-rockchip/ddr_rk3126.c
index d90da54f3e74475072548f39636fb5d8c994484e..4f8904b0ad8f01b80405d7514cea154887331cf7 100755 (executable)
--- a/arch/arm/mach-rockchip/ddr_rk3126.c
+++ b/arch/arm/mach-rockchip/ddr_rk3126.c
@@ -21,9 +21,9 @@
 #include <asm/tlbflush.h>
 #include <linux/cpu.h>
 #include <dt-bindings/clock/ddr.h>
+#include <linux/rockchip/cpu_axi.h>
 #include <linux/rockchip/cru.h>
 #include <linux/rk_fb.h>
-#include "cpu_axi.h"
 
 typedef uint32_t uint32;
 

diff --git a/arch/arm/mach-rockchip/ddr_rk3126b.c b/arch/arm/mach-rockchip/ddr_rk3126b.c
index 5e1bc097aee951ff3405cbe3713a6fa88625c318..9cba6f0fc722aaa78e9b04d20f3c28d7aad77000 100755 (executable)
--- a/arch/arm/mach-rockchip/ddr_rk3126b.c
+++ b/arch/arm/mach-rockchip/ddr_rk3126b.c
@@ -21,9 +21,9 @@
 #include <asm/tlbflush.h>
 #include <linux/cpu.h>
 #include <dt-bindings/clock/ddr.h>
+#include <linux/rockchip/cpu_axi.h>
 #include <linux/rockchip/cru.h>
 #include <linux/rk_fb.h>
-#include "cpu_axi.h"
 
 typedef uint32_t uint32;
 

diff --git a/arch/arm/mach-rockchip/ddr_rk32.c b/arch/arm/mach-rockchip/ddr_rk32.c
index 556035a39b860bf990022c787909006903a58b5f..c11c2bbbb8da94acd7f742b4f70c75b53e4c5c40 100755 (executable)
--- a/arch/arm/mach-rockchip/ddr_rk32.c
+++ b/arch/arm/mach-rockchip/ddr_rk32.c
@@ -18,9 +18,9 @@
 #include <asm/tlbflush.h>
 #include <linux/cpu.h>
 #include <dt-bindings/clock/ddr.h>
+#include <linux/rockchip/cpu_axi.h>
 #include <linux/rockchip/cru.h>
 #include <linux/rk_fb.h>
-#include "cpu_axi.h"
 
 typedef uint32_t uint32;
 

diff --git a/arch/arm/mach-rockchip/rk3036.c b/arch/arm/mach-rockchip/rk3036.c
index e0f0a25bd1b5dbcefed4f2d88ef26154d6b2a7aa..89b3850da268bba9d6d8a829800ff05b31dec45b 100755 (executable)
--- a/arch/arm/mach-rockchip/rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036.c
@@ -26,6 +26,7 @@
 #include <linux/wakeup_reason.h>
 #include <linux/rockchip/common.h>
 #include <linux/rockchip/cpu.h>
+#include <linux/rockchip/cpu_axi.h>
 #include <linux/rockchip/cru.h>
 #include <linux/rockchip/dvfs.h>
 #include <linux/rockchip/grf.h>
@@ -35,7 +36,6 @@
 #include <asm/cputype.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include "cpu_axi.h"
 #include "loader.h"
 #define CPU 3036
 #include "sram.h"

diff --git a/arch/arm/mach-rockchip/rk312x.c b/arch/arm/mach-rockchip/rk312x.c
index aaef664d42f9509b8dc3e37dd71f36f5b8fa1c53..91255c901ca1abc4c5c0348b4694df725a095ac9 100755 (executable)
--- a/arch/arm/mach-rockchip/rk312x.c
+++ b/arch/arm/mach-rockchip/rk312x.c
@@ -23,6 +23,7 @@
 #include <linux/of_platform.h>
 #include <linux/rockchip/common.h>
 #include <linux/rockchip/cpu.h>
+#include <linux/rockchip/cpu_axi.h>
 #include <linux/rockchip/cru.h>
 #include <linux/rockchip/dvfs.h>
 #include <linux/rockchip/grf.h>
@@ -32,7 +33,6 @@
 #include <asm/cputype.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include "cpu_axi.h"
 #include "loader.h"
 #include "rk3126b.h"
 #define CPU 312x

diff --git a/arch/arm/mach-rockchip/rk3188.c b/arch/arm/mach-rockchip/rk3188.c
index 8d4aaae5321ee97e678403a3e3fb3419e19254bb..093dce7ef688db934e0550549aa61273720e80de 100755 (executable)
--- a/arch/arm/mach-rockchip/rk3188.c
+++ b/arch/arm/mach-rockchip/rk3188.c
@@ -24,13 +24,13 @@
 #include <linux/rockchip/dvfs.h>
 #include <linux/rockchip/common.h>
 #include <linux/rockchip/cpu.h>
+#include <linux/rockchip/cpu_axi.h>
 #include <linux/rockchip/cru.h>
 #include <linux/rockchip/grf.h>
 #include <linux/rockchip/iomap.h>
 #include <linux/rockchip/pmu.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include "cpu_axi.h"
 #include "loader.h"
 #include "sram.h"
 

diff --git a/arch/arm/mach-rockchip/rk3288.c b/arch/arm/mach-rockchip/rk3288.c
index 04af8772d603e516ca6a7b2d5a20cac8a8a46a70..0a768a98ba06a68388b119a3236dedaff66d87ec 100755 (executable)
--- a/arch/arm/mach-rockchip/rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288.c
@@ -25,6 +25,7 @@
 #include <linux/of_platform.h>
 #include <linux/rockchip/common.h>
 #include <linux/rockchip/cpu.h>
+#include <linux/rockchip/cpu_axi.h>
 #include <linux/rockchip/cru.h>
 #include <linux/rockchip/dvfs.h>
 #include <linux/rockchip/grf.h>
@@ -35,7 +36,6 @@
 #include <asm/cputype.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include "cpu_axi.h"
 #include "loader.h"
 #define CPU 3288
 #include "sram.h"

diff --git a/include/linux/rockchip/cpu_axi.h b/include/linux/rockchip/cpu_axi.h
new file mode 100644 (file)
index 0000000..9af5a7a
--- /dev/null
+++ b/include/linux/rockchip/cpu_axi.h
@@ -0,0 +1,128 @@
+#ifndef __CPU_AXI_H
+#define __CPU_AXI_H
+
+#define CPU_AXI_QOS_PRIORITY    0x08
+#define CPU_AXI_QOS_MODE        0x0c
+#define CPU_AXI_QOS_BANDWIDTH   0x10
+#define CPU_AXI_QOS_SATURATION  0x14
+#define CPU_AXI_QOS_EXTCONTROL  0x18
+
+#define CPU_AXI_QOS_MODE_NONE           0
+#define CPU_AXI_QOS_MODE_FIXED          1
+#define CPU_AXI_QOS_MODE_LIMITER        2
+#define CPU_AXI_QOS_MODE_REGULATOR      3
+
+#define CPU_AXI_QOS_PRIORITY_LEVEL(h, l) \
+       ((((h) & 3) << 8) | (((h) & 3) << 2) | ((l) & 3))
+#define CPU_AXI_SET_QOS_PRIORITY(h, l, base) \
+       writel_relaxed(CPU_AXI_QOS_PRIORITY_LEVEL(h, l), base + CPU_AXI_QOS_PRIORITY)
+
+#define CPU_AXI_SET_QOS_MODE(mode, base) \
+       writel_relaxed((mode) & 3, base + CPU_AXI_QOS_MODE)
+
+#define CPU_AXI_SET_QOS_BANDWIDTH(bandwidth, base) \
+       writel_relaxed((bandwidth) & 0x7ff, base + CPU_AXI_QOS_BANDWIDTH)
+
+#define CPU_AXI_SET_QOS_SATURATION(saturation, base) \
+       writel_relaxed((saturation) & 0x3ff, base + CPU_AXI_QOS_SATURATION)
+
+#define CPU_AXI_SET_QOS_EXTCONTROL(extcontrol, base) \
+       writel_relaxed((extcontrol) & 7, base + CPU_AXI_QOS_EXTCONTROL)
+
+#define CPU_AXI_QOS_NUM_REGS 5
+#define CPU_AXI_SAVE_QOS(array, base) do { \
+       array[0] = readl_relaxed(base + CPU_AXI_QOS_PRIORITY); \
+       array[1] = readl_relaxed(base + CPU_AXI_QOS_MODE); \
+       array[2] = readl_relaxed(base + CPU_AXI_QOS_BANDWIDTH); \
+       array[3] = readl_relaxed(base + CPU_AXI_QOS_SATURATION); \
+       array[4] = readl_relaxed(base + CPU_AXI_QOS_EXTCONTROL); \
+} while (0)
+#define CPU_AXI_RESTORE_QOS(array, base) do { \
+       writel_relaxed(array[0], base + CPU_AXI_QOS_PRIORITY); \
+       writel_relaxed(array[1], base + CPU_AXI_QOS_MODE); \
+       writel_relaxed(array[2], base + CPU_AXI_QOS_BANDWIDTH); \
+       writel_relaxed(array[3], base + CPU_AXI_QOS_SATURATION); \
+       writel_relaxed(array[4], base + CPU_AXI_QOS_EXTCONTROL); \
+} while (0)
+
+#define RK3188_CPU_AXI_DMAC_QOS_VIRT    (RK_CPU_AXI_BUS_VIRT + 0x1000)
+#define RK3188_CPU_AXI_CPU0_QOS_VIRT    (RK_CPU_AXI_BUS_VIRT + 0x2000)
+#define RK3188_CPU_AXI_CPU1R_QOS_VIRT   (RK_CPU_AXI_BUS_VIRT + 0x2080)
+#define RK3188_CPU_AXI_CPU1W_QOS_VIRT   (RK_CPU_AXI_BUS_VIRT + 0x2100)
+#define RK3188_CPU_AXI_PERI_QOS_VIRT    (RK_CPU_AXI_BUS_VIRT + 0x4000)
+#define RK3188_CPU_AXI_GPU_QOS_VIRT     (RK_CPU_AXI_BUS_VIRT + 0x5000)
+#define RK3188_CPU_AXI_VPU_QOS_VIRT     (RK_CPU_AXI_BUS_VIRT + 0x6000)
+#define RK3188_CPU_AXI_LCDC0_QOS_VIRT   (RK_CPU_AXI_BUS_VIRT + 0x7000)
+#define RK3188_CPU_AXI_CIF0_QOS_VIRT    (RK_CPU_AXI_BUS_VIRT + 0x7080)
+#define RK3188_CPU_AXI_IPP_QOS_VIRT     (RK_CPU_AXI_BUS_VIRT + 0x7100)
+#define RK3188_CPU_AXI_LCDC1_QOS_VIRT   (RK_CPU_AXI_BUS_VIRT + 0x7180)
+#define RK3188_CPU_AXI_CIF1_QOS_VIRT    (RK_CPU_AXI_BUS_VIRT + 0x7200)
+#define RK3188_CPU_AXI_RGA_QOS_VIRT     (RK_CPU_AXI_BUS_VIRT + 0x7280)
+
+/* service core */
+#define RK3288_SERVICE_CORE_VIRT                RK_CPU_AXI_BUS_VIRT
+#define RK3288_CPU_AXI_CPUM_R_QOS_VIRT          (RK3288_SERVICE_CORE_VIRT + 0x80)
+#define RK3288_CPU_AXI_CPUM_W_QOS_VIRT          (RK3288_SERVICE_CORE_VIRT + 0x100)
+#define RK3288_CPU_AXI_CPUP_QOS_VIRT            (RK3288_SERVICE_CORE_VIRT + 0x0)
+/* service dmac */
+#define RK3288_SERVICE_DMAC_VIRT                (RK3288_SERVICE_CORE_VIRT + RK3288_SERVICE_CORE_SIZE)
+#define RK3288_CPU_AXI_BUS_DMAC_QOS_VIRT        (RK3288_SERVICE_DMAC_VIRT + 0x0)
+#define RK3288_CPU_AXI_CCP_QOS_VIRT             (RK3288_SERVICE_DMAC_VIRT + 0x180)
+#define RK3288_CPU_AXI_CRYPTO_QOS_VIRT          (RK3288_SERVICE_DMAC_VIRT + 0x100)
+#define RK3288_CPU_AXI_CCS_QOS_VIRT             (RK3288_SERVICE_DMAC_VIRT + 0x200)
+#define RK3288_CPU_AXI_HOST_QOS_VIRT            (RK3288_SERVICE_DMAC_VIRT + 0x80)
+/* service gpu */
+#define RK3288_SERVICE_GPU_VIRT                 (RK3288_SERVICE_DMAC_VIRT + RK3288_SERVICE_DMAC_SIZE)
+#define RK3288_CPU_AXI_GPU_R_QOS_VIRT           (RK3288_SERVICE_GPU_VIRT + 0x0)
+#define RK3288_CPU_AXI_GPU_W_QOS_VIRT           (RK3288_SERVICE_GPU_VIRT + 0x80)
+/* service peri */
+#define RK3288_SERVICE_PERI_VIRT                (RK3288_SERVICE_GPU_VIRT + RK3288_SERVICE_GPU_SIZE)
+#define RK3288_CPU_AXI_PERI_QOS_VIRT            (RK3288_SERVICE_PERI_VIRT + 0x0)
+/* service bus */
+#define RK3288_SERVICE_BUS_VIRT                 (RK3288_SERVICE_PERI_VIRT + RK3288_SERVICE_PERI_SIZE)
+/* service vio */
+#define RK3288_SERVICE_VIO_VIRT                 (RK3288_SERVICE_BUS_VIRT + RK3288_SERVICE_BUS_SIZE)
+#define RK3288_CPU_AXI_VIO0_IEP_QOS_VIRT        (RK3288_SERVICE_VIO_VIRT + 0x500)
+#define RK3288_CPU_AXI_VIO0_VIP_QOS_VIRT        (RK3288_SERVICE_VIO_VIRT + 0x480)
+#define RK3288_CPU_AXI_VIO0_VOP_QOS_VIRT        (RK3288_SERVICE_VIO_VIRT + 0x400)
+#define RK3288_CPU_AXI_VIO1_ISP_R_QOS_VIRT      (RK3288_SERVICE_VIO_VIRT + 0x900)
+#define RK3288_CPU_AXI_VIO1_ISP_W0_QOS_VIRT     (RK3288_SERVICE_VIO_VIRT + 0x100)
+#define RK3288_CPU_AXI_VIO1_ISP_W1_QOS_VIRT     (RK3288_SERVICE_VIO_VIRT + 0x180)
+#define RK3288_CPU_AXI_VIO1_VOP_QOS_VIRT        (RK3288_SERVICE_VIO_VIRT + 0x0)
+#define RK3288_CPU_AXI_VIO2_RGA_R_QOS_VIRT      (RK3288_SERVICE_VIO_VIRT + 0x800)
+#define RK3288_CPU_AXI_VIO2_RGA_W_QOS_VIRT      (RK3288_SERVICE_VIO_VIRT + 0x880)
+/* service video */
+#define RK3288_SERVICE_VIDEO_VIRT               (RK3288_SERVICE_VIO_VIRT + RK3288_SERVICE_VIO_SIZE)
+#define RK3288_CPU_AXI_VIDEO_QOS_VIRT           (RK3288_SERVICE_VIDEO_VIRT + 0x0)
+/* service hevc */
+#define RK3288_SERVICE_HEVC_VIRT                (RK3288_SERVICE_VIDEO_VIRT + RK3288_SERVICE_VIDEO_SIZE)
+#define RK3288_CPU_AXI_HEVC_R_QOS_VIRT          (RK3288_SERVICE_HEVC_VIRT + 0x0)
+#define RK3288_CPU_AXI_HEVC_W_QOS_VIRT          (RK3288_SERVICE_HEVC_VIRT + 0x100)
+
+#define RK312X_CPU_AXI_QOS_NUM_REGS 4
+#define RK312X_CPU_AXI_SAVE_QOS(array, base) do { \
+       array[0] = readl_relaxed(base + CPU_AXI_QOS_PRIORITY); \
+       array[1] = readl_relaxed(base + CPU_AXI_QOS_MODE); \
+       array[2] = readl_relaxed(base + CPU_AXI_QOS_BANDWIDTH); \
+       array[3] = readl_relaxed(base + CPU_AXI_QOS_SATURATION); \
+} while (0)
+#define RK312X_CPU_AXI_RESTORE_QOS(array, base) do { \
+       writel_relaxed(array[0], base + CPU_AXI_QOS_PRIORITY); \
+       writel_relaxed(array[1], base + CPU_AXI_QOS_MODE); \
+       writel_relaxed(array[2], base + CPU_AXI_QOS_BANDWIDTH); \
+       writel_relaxed(array[3], base + CPU_AXI_QOS_SATURATION); \
+} while (0)
+#define RK312X_SERVICE_VIO_VIRT                 (RK_CPU_AXI_BUS_VIRT + 0x7000)
+
+#define RK312X_CPU_AXI_VIO_RGA_QOS_VIRT        (RK312X_SERVICE_VIO_VIRT)
+#define RK312X_CPU_AXI_VIO_EBC_QOS_VIRT        (RK312X_SERVICE_VIO_VIRT + 0x80)
+#define RK312X_CPU_AXI_VIO_IEP_QOS_VIRT      (RK312X_SERVICE_VIO_VIRT + 0x100)
+#define RK312X_CPU_AXI_VIO_LCDC0_QOS_VIRT     (RK312X_SERVICE_VIO_VIRT + 0x180)
+#define RK312X_CPU_AXI_VIO_VIP0_QOS_VIRT     (RK312X_SERVICE_VIO_VIRT + 0x200)
+
+#define RK312X_SERVICE_GPU_VIRT                 (RK_CPU_AXI_BUS_VIRT + 0x5000)
+#define RK312X_CPU_AXI_GPU_QOS_VIRT        (RK312X_SERVICE_GPU_VIRT)
+
+#define RK312X_SERVICE_VIDEO_VIRT                 (RK_CPU_AXI_BUS_VIRT + 0x6000)
+#define RK312X_CPU_AXI_VIDEO_QOS_VIRT        (RK312X_SERVICE_VIDEO_VIRT)
+#endif