arm64: dts: rockchip: rk3328: hdmi enable inno-hdmi-phy driver

Change-Id: I3d4c6dfcaffeb6679666fcedf58e645d26205efa
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 48655ef0b71549480456b341973d6836174cc257..b859b6b3b1398939332c0f5d2beddc61e20e28ae 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -796,24 +796,18 @@
 
        hdmi: hdmi@ff3c0000 {
                compatible = "rockchip,rk3328-dw-hdmi";
-               reg = <0x0 0xff3c0000 0x0 0x20000>,
-                     <0x0 0xff430000 0x0 0x10000>;
+               reg = <0x0 0xff3c0000 0x0 0x20000>;
                reg-io-width = <4>;
                interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
-                            <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
-                            <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+                            <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru PCLK_HDMI>,
                         <&cru SCLK_HDMI_SFC>,
-                        <&cru PCLK_HDMIPHY>,
                         <&cru HCLK_VIO>;
                clock-names = "iahb",
                              "isfr",
-                             "pclk_hdmiphy",
                              "hclk_vio";
-               #clock-cells = <0>;
-               clock-output-names = "hdmi_phy";
-               assigned-clocks = <&cru HDMIPHY>;
-               assigned-clock-parents = <&hdmi>;
+               phys = <&hdmiphy>;
+               phy-names = "hdmi_phy";
                pinctrl-names = "default", "gpio";
                pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
                pinctrl-1 = <&i2c3_gpio>;
@@ -877,6 +871,18 @@
                status = "disabled";
        };
 
+       hdmiphy: hdmiphy@ff430000 {
+               compatible = "rockchip,rk3328-hdmi-phy";
+               reg = <0x0 0xff430000 0x0 0x10000>;
+               interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+               #phy-cells = <0>;
+               clocks = <&cru PCLK_HDMIPHY>, <&xin24m>;
+               clock-names = "sysclk", "refclk";
+               #clock-cells = <0>;
+               clock-output-names = "hdmi_phy";
+               status = "disabled";
+       };
+
        cru: clock-controller@ff440000 {
                compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
                reg = <0x0 0xff440000 0x0 0x1000>;