camsys: v0.e.0
authorddl <ddl@rock-chips.com>
Tue, 24 Jun 2014 07:24:06 +0000 (15:24 +0800)
committerddl <ddl@rock-chips.com>
Tue, 24 Jun 2014 07:24:27 +0000 (15:24 +0800)
drivers/media/video/rk_camsys/camsys_internal.h
drivers/media/video/rk_camsys/camsys_marvin.c

index 1ebb947158a816232c79bd6483bfeba0c430fc57..0634808f1204ecd8a4bf06999b1d8e5a0968c70a 100755 (executable)
 *        1) add flash_trigger_out control
 *v0.d.0:
 *        1) add Isp_SoftRst for rk3288;
+*v0.e.0:
+*        1) isp_clk 208.8M for 1lane, isp_clk 416.6M for 2lane;
 */
-#define CAMSYS_DRIVER_VERSION                   KERNEL_VERSION(0,0xd,0)
+#define CAMSYS_DRIVER_VERSION                   KERNEL_VERSION(0,0xe,0)
 
 
 #define CAMSYS_PLATFORM_DRV_NAME                "RockChip-CamSys"
index 74493356fb4706c3476c9af7aaf232c42a205ee6..07e5f124123afb89993b526890e60a30e9b45296 100755 (executable)
@@ -199,10 +199,20 @@ static int camsys_mrv_clkin_cb(void *ptr, unsigned int on)
 {
     camsys_dev_t *camsys_dev = (camsys_dev_t*)ptr;
     camsys_mrv_clk_t *clk = (camsys_mrv_clk_t*)camsys_dev->clk;
+    unsigned long isp_clk;
        
     if (on && !clk->in_on) {
                rockchip_set_system_status(SYS_STATUS_ISP);
 
+               if (on == 1) {
+                   isp_clk = 210000000;           
+               } else {
+                   isp_clk = 420000000;            
+               }
+
+               clk_set_rate(clk->isp,isp_clk);
+        clk_set_rate(clk->isp_jpe, isp_clk);
+
         clk_prepare_enable(clk->aclk_isp);
         clk_prepare_enable(clk->hclk_isp);
         clk_prepare_enable(clk->isp);
@@ -213,7 +223,7 @@ static int camsys_mrv_clkin_cb(void *ptr, unsigned int on)
 
         clk->in_on = true;
 
-        camsys_trace(1, "%s clock in turn on",dev_name(camsys_dev->miscdev.this_device));
+        camsys_trace(1, "%s clock(f: %ld Hz) in turn on",dev_name(camsys_dev->miscdev.this_device),isp_clk);
         camsys_mrv_reset_cb(ptr,1);
         udelay(100);
         camsys_mrv_reset_cb(ptr,0);