UPSTREAM: PCI: rockchip: remove the pointer to L1 substate cap

Per the errata of TRM, the RC can't support L1 substate, so we
need to remove the L1 substate cap as well as operation for
PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2.

Change-Id: If3e1e7ac46720c9487724f15b22905a02bebb7ca
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Tested-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
(am from git.kernel.org/cgit/linux/kernel/git/next/linux-next.git
commit 9d7598543b5fa2dacd7ccdffe9e03b578a9a03d1)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index f567518cb35c532433d4ba392f9b9f0fa0abcab5..f532bce88f1289de4bbbd4a3de514abde1b48c68 100644 (file)
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -148,6 +148,8 @@
 #define   PCIE_RC_CONFIG_LCS_LBMS              BIT(30)
 #define   PCIE_RC_CONFIG_LCS_LAMS              BIT(31)
 #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)
 #define   PCIE_RC_CONFIG_LCS_LBMS              BIT(30)
 #define   PCIE_RC_CONFIG_LCS_LAMS              BIT(31)
 #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)

+#define PCIE_RC_CONFIG_THP_CAP         (PCIE_RC_CONFIG_BASE + 0x274)
+#define   PCIE_RC_CONFIG_THP_CAP_NEXT_MASK     GENMASK(31, 20)

 
 #define PCIE_CORE_AXI_CONF_BASE                0xc00000
 #define PCIE_CORE_OB_REGION_ADDR0      (PCIE_CORE_AXI_CONF_BASE + 0x0)
 
 #define PCIE_CORE_AXI_CONF_BASE                0xc00000
 #define PCIE_CORE_OB_REGION_ADDR0      (PCIE_CORE_AXI_CONF_BASE + 0x0)


@@ -528,15 +530,6 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
                return err;
        }
 
                return err;
        }
 

-       /*
-        * We need to read/write PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 before
-        * enabling ASPM.  Otherwise L1PwrOnSc and L1PwrOnVal isn't
-        * reliable and enabling ASPM doesn't work.  This is a controller
-        * bug we need to work around.
-        */
-       status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
-       rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
-

        /* Fix the transmitted FTS count desired to exit from L0s. */
        status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
        status = (status & PCIE_CORE_CTRL_PLC1_FTS_MASK) |
        /* Fix the transmitted FTS count desired to exit from L0s. */
        status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
        status = (status & PCIE_CORE_CTRL_PLC1_FTS_MASK) |


@@ -614,6 +607,12 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
        rockchip_pcie_write(rockchip,
                            PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
                            PCIE_RC_CONFIG_RID_CCR);
        rockchip_pcie_write(rockchip,
                            PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
                            PCIE_RC_CONFIG_RID_CCR);

+
+       /* Clear THP cap's next cap pointer to remove L1 substate cap */
+       status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_THP_CAP);
+       status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK;
+       rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP);
+

        rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
 
        rockchip_pcie_write(rockchip,
        rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
 
        rockchip_pcie_write(rockchip,