CHROMIUM: drm: rockchip/dw_hdmi: introduce werid audio tmds_n table

There are some rates that would be ranged for better clock jitter at
Chrome OS tree, like 25.175Mhz would range to 25.170732Mhz.

But due to the clock is aglined to KHz in struct drm_display_mode,
this would bring some inaccurate error if we still run the compute_n
math, so let's just code an const table for it until we can actually
get the right clock rate.

Change-Id: Ief14b7c9bffa95ff3b173925f3e1bd795625320d
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/316280
Commit-Ready: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>

diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index f168f4b457b4dd9ae61aba35188ded884bddb4ab..a201e8422e278ee62e5a38c776b3bb021f3b9efb 100644 (file)
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -90,6 +90,31 @@ static const int dw_hdmi_rates[] = {
        297000000,
 };
 
+/*
+ * There are some rates that would be ranged for better clock jitter at
+ * Chrome OS tree, like 25.175Mhz would range to 25.170732Mhz. But due
+ * to the clock is aglined to KHz in struct drm_display_mode, this would
+ * bring some inaccurate error if we still run the compute_n math, so
+ * let's just code an const table for it until we can actually get the
+ * right clock rate.
+ */
+static const struct dw_hdmi_audio_tmds_n rockchip_werid_tmds_n_table[] = {
+       /* 25176471 for 25.175 MHz = 428000000 / 17. */
+       { .tmds = 25177000, .n_32k = 4352, .n_44k1 = 14994, .n_48k = 6528, },
+       /* 57290323 for 57.284 MHz */
+       { .tmds = 57291000, .n_32k = 3968, .n_44k1 = 4557, .n_48k = 5952, },
+       /* 74437500 for 74.44 MHz = 297750000 / 4 */
+       { .tmds = 74438000, .n_32k = 8192, .n_44k1 = 18816, .n_48k = 4096, },
+       /* 118666667 for 118.68 MHz */
+       { .tmds = 118667000, .n_32k = 4224, .n_44k1 = 5292, .n_48k = 6336, },
+       /* 121714286 for 121.75 MHz */
+       { .tmds = 121715000, .n_32k = 4480, .n_44k1 = 6174, .n_48k = 6272, },
+       /* 136800000 for 136.75 MHz */
+       { .tmds = 136800000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
+       /* End of table */
+       { .tmds = 0,         .n_32k = 0,    .n_44k1 = 0,    .n_48k = 0, },
+};
+
 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
        {
                30666000, {
@@ -386,6 +411,7 @@ static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
        .cur_ctr    = rockchip_cur_ctr,
        .phy_config = rockchip_phy_config,
        .dev_type   = RK3288_HDMI,
+       .tmds_n_table = rockchip_werid_tmds_n_table,
 };
 
 static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {